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under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer description 1 ------table of contents------ description the m30201 group of single-chip microcomputers are built using the high-performance silicon gate cmos process using a m16c/60 series cpu core. m30201 group is packaged in a 52-pin plastic molded sdip, or 56-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, they are capable of execut- ing instructions at high speed. the m30201 group includes a wide range of products with different internal memory types and sizes and various package types. features ? basic machine instructions .................. compatible with the m16c/60 series ? memory capacity .................................. rom/ram (see figure 1.4. rom expansion.) ? shortest instruction execution time ...... 100ns (f(x in )=10mhz) ? supply voltage ..................................... 4.0 to 5.5v (f(x in )=10mhz) :mask rom version 2.7 to 5.5v (f(x in )=7mhz with software one-wait):mask rom version 4.0 to 5.5v (f(x in )=10mhz) :flash memory version ? interrupts .............................................. 9 internal and 3 external interrupt sources, 4 software (including key input interrupt) ? multifunction 16-bit timer ...................... timer a x 1, timer b x 2, timer x x 3 ? clock output ? serial i/o .............................................. 1 channel for uart or clock synchronous, 1 for uart ? a-d converter ....................................... 10 bits x 8 channels (expandable up to 13 channels) ? watchdog timer .................................... 1 line ? programmable i/o ............................... 43 lines ? led drive ports .................................... 8 ports ? clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) applications home appliances, audio, office equipment, automobiles timer ............................................................. 37 serial i/o ....................................................... 64 a-d converter ............................................... 78 programmable i/o ports ............................... 88 electric characteristics ................................. 95 flash memory version ................................. 126 central processing unit (cpu) ..................... 12 reset ............................................................. 15 clock generating circuit ............................... 19 protection ...................................................... 26 interrupts ....................................................... 27 watchdog timer ............................................ 35 specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer description 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 v ref x in x out p5 0 /t x d 0 /an 50 p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 v ss reset v cc cnv ss p5 1 /r x d 0 /an 51 p5 2 /clk 0 /an 52 av ss p4 5 /tx2 inout p7 0 /tb0 in /x cout p7 1 /tb1 in /x cin p5 4 /ck out /an 54 p5 3 /clks/an 53 av cc p0 7 /ki 7 p0 6 /ki 6 p0 5 /ki 5 p0 4 /ki 4 p0 3 /ki 3 p0 2 /ki 2 p0 1 /ki 1 p1 0 (led 0 ) p1 1 (led 1 ) p1 2 (led 2 ) p1 3 (led 3 ) p1 4 (led 4 ) p1 5 (led 5 ) p1 6 (led 6 ) p1 7 (led 7 ) m30201mx-xxxsp M30201MXT-XXXSP m30201f6sp m30201f6tsp p0 0 /ki 0 p3 0 p3 1 p3 2 p3 3 p3 4 p3 5 p4 0 /ta0 in /t x d 1 p4 1 /ta0 out p4 2 /r x d 1 p4 4 /int 1 /tx1 inout p4 3 /int 0 /tx0 inout pin configuration figures 1.1 to 1.2 show the pin configurations (top view). pin configuration (top view) package: 52p4b figure 1.1. pin configuration for the m30201 group (shrink dip product) (top view)
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer description 3 x in x out p5 0 /t x d 0 /an 50 p6 7 /an 7 v ss reset v cc cnv ss p5 1 /r x d 0 /an 51 p5 2 /clk 0 /an 52 p4 5 /tx2 inout p7 1 /tb1 in /x cin p7 0 /tb0 in /x cout p4 1 /ta0 out p4 0 /ta0 in /t x d 1 p4 2 /r x d 1 p5 4 /ck out /an 54 p5 3 /clks/an 53 v ref p6 0 /an 0 p6 1 /an 1 av ss av cc p1 0 (led 0 ) p1 4 (led 4 ) m30201mx-xxxfp m30201mxt-xxxfp m30201f6fp m30201f6tfp n.c. n.c. n.c. n.c. p0 0 /ki 0 p6 2 /an 2 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 p0 1 /ki 1 p0 2 /ki 2 p0 3 /ki 3 p0 4 /ki 4 p0 5 /ki 5 p0 6 /ki 6 p0 7 /ki 7 p1 1 (led 1 ) p1 2 (led 2 ) p1 3 (led 3 ) p1 5 (led 5 ) p1 6 (led 6 ) p1 7 (led 7 ) p3 0 p3 1 p3 2 p3 3 p3 4 p3 5 p4 4 /int 1 /tx1 inout p4 3 /int 0 /tx0 inout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 27 28 figure 1.2. pin configuration for the m30201 group (qfp product) (top view) package: 56p6s-a pin configuration (top view)
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer description 4 figure 1.3. block diagram for the m30201 group aaaaa aaaaa timer timer ta0 (16 bits) timer tb0 (16 bits) timer tb1 (16 bits) timer tx0 (16 bits) timer tx1 (16 bits) timer tx2 (16 bits) internal peripheral functions watchdog timer (15 bits) a-d converter (10 bits x 8 channels expandable up to 13 channels) uart/clock synchronous si/o (8 bits x 1 channel) system clock generator x in -x out x cin -x cout m16c/60 series16-bit cpu core i/o ports port p0 8 port p1 8 port p3 6 port p4 6 port p5 5 port p6 8 r0l r0h r1h r1l r2 r3 a0 a1 fb r0l r0h r1h r1l r2 r3 a0 a1 fb registers isp usp stack pointer vector table intb uart (8 bits x 1 channel) multiplier 2 port p7 aaaaaaa a aaaaa a a aaaaa a a aaaaa a aaaaaaa memory rom (note 1) ram (note 2) sb flg pc program counter note 1: rom size depends on mcu type. note 2: ram size depends on mcu type. block diagram figure 1.3 is a block diagram of the m30201 group.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer description 5 table 1.1. performance outline of m30201 group performance outline table 1.1 is performance outline of m30201 group. item performance number of basic instructions 91 instructions shortest instruction execution time 100ns (f(x in )=10mhz memory rom (see figure 4. rom expansion.) capacity ram (see figure 4. rom expansion.) i/o port p0 to p7 43 lines multifunction ta0 16 bits x 1 timer tb0, tb1 16 bits x 2 tx0, tx1, tx2 16 bits x 3 serial i/o uart0 (uart or clock synchronous) x 1 uart1 uart x 1 a-d converter 10 bits x 8 channels (expandable up to 13 channels) watchdog timer 15 bits x 1 (with prescaler) interrupt 9 internal and 3 external sources, 4 software sources clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) supply voltage 4.0 to 5.5v (f(x in )=10mhz) :mask rom version 2.7 to 5.5v (f(x in )=7mhz with software one-wait) :mask rom version 4.0 to 5.5v (f(x in )=10mhz) :flash memory version power consumption 18mw (f(x in )=7mhz with software one-wait, vcc=3v) :mask rom version 95mw (f(x in )=10mhz no wait, vcc=5v) :flash memory version i/o i/o withstand voltage 5v characteristics output current 5ma (15ma:led drive port) device configuration cmos silicon gate package 52-pin plastic mold sdip 56-pin plastic mold qfp
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer description 6 mitsubishi plans to release the following products in the m30201 group: (1) support for mask rom version and flash memory version (2) rom capacity (3) package 52p4b : plastic molded sdip (mask rom version and flash memory version) 56p6s-a : plastic molded qfp (mask rom version and flash memory version) ram size (byte) 1k 16k 32k m30201m4-xxxsp/fp m30201m4t-xxxsp/fp 512 rom size (byte) m30201m2-xxxsp/fp m30201m2t-xxxsp/fp under development under planning 2k m30201f6sp/fp m30201f6tsp/fp 48k under development figure 1.4. rom expansion july 1998 package type: sp : package 52p4b fp : package 56p6s-a rom no. omitted for flash memory version shows difference of characteristics and usage etc: nothing : common t : automobiles memory type: m : mask rom version f : flash memory version type no. m 3 0 2 0 1 m 4 t ? x x x s p m16c/20 group m16c family shows pin count, etc (the value itself has no specific meaning) rom capacity: 2 : 16k bytes 4 : 32k bytes 6 : 48k bytes figure 1.5. type no., memory size, and package
pin description under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 7 v cc , v ss cnv ss x in x out av cc av ss v ref p0 0 to p0 7 p1 0 to p1 7 p3 0 to p3 5 p4 0 to p4 5 signal name power supply input cnv ss reset input clock input clock output analog power supply input reference voltage input i/o port p0 i/o port p1 i/o port p3 i/o port p4 supply 2.7 to 5.5 v to the v cc pin. supply 0 v to the v ss pin. function connect it to the v ss pin. a ?? on this input resets the microcomputer. these pins are provided for the main clock generating circuit. connect a ceramic resonator or crystal between the x in and the x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. this pin is a power supply input for the a-d converter. connect it to v cc . this pin is a power supply input for the a-d converter. connect it to v ss . this pin is a reference voltage input for the a-d converter. this is an 8-bit cmos i/o port. it has an input/output port direction register that allows the user to set each pin for input or output individually. when set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. this is an 8-bit i/o port equivalent to p0. this is a 6-bit i/o port equivalent to p0. this is a 6-bit i/o port equivalent to p0. the p4 0 pin is shared with timer a0 input and serial i/o output txd1. the p4 1 pin is shared with timer a0 output. the p4 2 pin is shared with serial i/o input rxd1. the p4 3 pin is shared with external interrupt int0 and timer x0 input/output tx0 inout . the p4 4 pin is shared with external interrupt int1 and timer x1 input/output tx1 inout . the p4 5 pin is shared with timer x2 input/output tx2 inout . pin name input input input output input input/output input/output i/o type analog power supply input input/output input/output reset i/o port p5 input/output input/output input/output i/o port p6 i/o port p7 p5 0 to p5 4 p6 0 to p6 7 p7 0 to p7 1 this is a 5-bit i/o port equivalent to p0. the p5 0 , p5 1 , p5 2 , and p5 3 pins are shared with serial i/o pins txd 0 , rxd 0 , clk 0 , and clks. the p5 4 pin is shared with clock output clk out . also, these pins are shared with analog input pins an 50 through an 54 . this is an 8-bit i/o port equivalent to p0. these pins are shared with analog input pins an 0 through an 7 . this is a 2-bit i/o port equivalent to p0 . these pins are used for input/output to and from the oscillator circuit for the clock. connect a crystal oscillator between the x cin and the x cout pins. pin description
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer memory 8 operation of functional blocks the m30201 accommodates certain units in a single chip. these units include rom and ram to store instructions and data and the central processing unit (cpu) to execute arithmetic/logic operations. also included are peripheral units such as timers, serial i/o, a-d converter, and i/o ports. the following explains each unit. memory figure 1.6 is a memory map of the m30201. the address space extends the 1m bytes from address 00000 16 to fffff 16 . from fffff 16 down is rom. for example, in the m30201m4-xxxfp, there is 32k bytes of internal rom from f8000 16 to fffff 16 . the vector table for fixed interrupts such as the reset are mapped to fffdc 16 to fffff 16 . the starting address of the interrupt routine is stored here. the address of the vector table for timer interrupts, etc., can be set as desired using the internal register (intb). see the section on interrupts for details. from 00400 16 up is ram. for example, in the m30201m4-xxxfp, there is 1k byte of internal ram from 00400 16 to 007ff 16 . in addition to storing data, the ram also stores the stack used when calling subrou- tines and when interrupts are generated. the sfr area is mapped to 00000 16 to 003ff 16 . this area accommodates the control registers for periph- eral devices such as i/o ports, a-d converter, serial i/o, and timers, etc. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. the special page vector table is mapped to ffe00 16 to fffdb 16 . if the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. figure 1.6. memory map 00000 16 yyyyy 16 fffff 16 00400 16 xxxxx 16 internal rom area sfr area for details, see figures 1.7 to 1.8 internal ram area ffe00 16 fffdc 16 fffff 16 undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc address xxxxx 16 007ff 16 f8000 16 005ff 16 fc000 16 m30201m2 m30201m4 type no. address yyyyy 16 00bff 16 f4000 16 m30201f6
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer memory 9 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 watchdog timer start register (wdts) watchdog timer control register (wdc) processor mode register 0 (pm0) address match interrupt register 0 (rmad0) address match interrupt register 1 (rmad1) system clock control register 0 (cm0) system clock control register 1 (cm1) address match interrupt enable register (aier) protect register (prcr) processor mode register 1(pm1) timer x0 interrupt control register (tx0ic) uart0 transmit interrupt control register (s0tic) timer a0 interrupt control register (ta0ic) timer x1 interrupt control register (tx1ic) uart0 receive interrupt control register (s0ric) uart1 transmit interrupt control register (s1tic) uart1 receive interrupt control register (s1ric) key input interrupt control register (kupic) a-d conversion interrupt control register (adic) int1 interrupt control register (int1ic) timer b0 interrupt control register (tb0ic) timer x2 interrupt control register (tx2ic) int0 interrupt control register (int0ic) timer b1 interrupt control register (tb1ic) figure 1.7. location of peripheral unit control registers (1)
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer memory 10 figure 1.8. location of peripheral unit control registers (2) 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 timer a0 (ta0) timer x0 (tx0) timer x1 (tx1) timer b0 (tb0) timer b1 (tb1) count start flag (tabsr) one-shot start flag (onsf) timer a0 mode register (ta0mr) timer x0 mode register (tx0mr) timer x1 mode register (tx1mr) timer b0 mode register (tb0mr) timer b1 mode register (tb1mr) up-down flag (udf) timer x2 (tx2) clock divided counter (cdc) timer x2 mode register (tx2mr) trigger select register (trgsr) clock prescaler reset flag (cpsrf) uart0 transmit/receive mode register (u0mr) uart0 transmit buffer register (u0tb) uart0 receive buffer register (u0rb) uart1 transmit/receive mode register (u1mr) uart1 transmit buffer register (u1tb) uart1 receive buffer register (u1rb) uart0 bit rate generator (u0brg) uart0 transmit/receive control register 0 (u0c0) uart0 transmit/receive control register 1 (u0c1) uart1 bit rate generator (u1brg) uart1 transmit/receive control register 0 (u1c0) uart1 transmit/receive control register 1 (u1c1) uart transmit/receive control register 2 (ucon) flash memory control register 0 (fcon0) (note) flash memory control register 1 (fcon1) (note) flash command register (fcmd) (note) note: this re g ister is onl y exist in flash memor y version. 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 a-d register 7 (ad7) a-d register 0 (ad0) a-d register 1 (ad1) a-d register 2 (ad2) a-d register 3 (ad3) a-d register 4 (ad4) a-d register 5 (ad5) a-d register 6 (ad6) port p0 (p0) port p0 direction register (pd0) port p1 (p1) port p1 direction register (pd1) port p2 (p2) (reserved) port p2 direction register (pd2) (reserved) port p3 (p3) port p3 direction register (pd3) port p4 (p4) port p4 direction register (pd4) port p5 (p5) port p5 direction register (pd5) port p6 (p6) port p6 direction register (pd6) port p7 (p7) port p7 direction register (pd7) pull-up control register 0 (pur0) pull-up control register 1 (pur1) port p1 drive control register (drr) a-d control register 0 (adcon0) a-d control register 1 (adcon1) a-d control register 2 (adcon2)
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer cpu 11 central processing unit (cpu) the cpu has a total of 13 registers shown in figure 1.9. seven of these registers (r0, r1, r2, r3, a0, a1, and fb) come in two sets; therefore, these have two register banks. (1) data registers (r0, r0h, r0l, r1, r1h, r1l, r2, and r3) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h, r1h), and low-order bits as (r0l, r1l). in some instructions, registers r2 and r0, as well as r3 and r1 can use as 32-bit data registers (r2r0, r3r1). (2) address registers (a0 and a1) address registers (a0 and a1) are configured with 16 bits, and have functions equivalent to those of data registers. these registers can also be used for address register indirect addressing and address register relative addressing. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). figure 1.9. central processing unit register aaaaaa aaaaaa h l b15 b8 b7 b0 r0 (note) aaaaaa aaaaaa h l b15 b8 b7 b0 r1 (note) r2 (note) aaaaaa aaaaaa b15 b0 r3 (note) aaaaaa aaaaaa b15 b0 a0 (note) aaaaaa aaaaaa b15 b0 a1 (note) aaaaaa aaaaaa b15 b0 fb (note) aaaaaa aaaaaa b15 b0 data registers address registers frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 h l program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register pc intb usp isp sb flg note: these registers consist of two register banks. aa aa aa aa a a aa aa aaaaaa aaaaaa aa aa aa aa a a aa aa aa aa c d z s b o i u ipl
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer cpu 12 (3) frame base register (fb) frame base register (fb) is configured with 16 bits, and is used for fb relative addressing. (4) program counter (pc) program counter (pc) is configured with 20 bits, indicating the address of an instruction to be executed. (5) interrupt table register (intb) interrupt table register (intb) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) stack pointer (usp/isp) stack pointer comes in two types: user stack pointer (usp) and interrupt stack pointer (isp), each config- ured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at the position of bit 7 in the flag register (flg). (7) static base register (sb) static base register (sb) is configured with 16 bits, and is used for sb relative addressing. (8) flag register (flg) flag register (flg) is configured with 11 bits, each bit is used as a flag. figure 1.10 shows the flag register (flg). the following explains the function of each flag: ? bit 0: carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ? bit 1: debug flag (d flag) this flag enables a single-step interrupt. when this flag is 1, a single-step interrupt is generated after instruction execution. this flag is cleared to 0 when the interrupt is acknowledged. ? bit 2: zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, cleared to 0. ? bit 3: sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, cleared to 0. ? bit 4: register bank select flag (b flag) this flag chooses a register bank. register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. ? bit 5: overflow flag (o flag) this flag is set to 1 when an arithmetic operation resulted in overflow; otherwise, cleared to 0. ? bit 6: interrupt enable flag (i flag) this flag enables a maskable interrupt. an interrupt is disabled when this flag is 0, and is enabled when this flag is 1. this flag is cleared to 0 when the interrupt is acknowledged.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer cpu 13 ? bit 7: stack pointer select flag (u flag) interrupt stack pointer (isp) is selected when this flag is 0 ; user stack pointer (usp) is selected when this flag is 1. this flag is cleared to 0 when a hardware interrupt is acknowledged or an int instruction of software interrupt nos. 0 to 31 is executed. ? bits 8 to 11: reserved area ? bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. ? bit 15: reserved area the c, z, s, and o flags are changed when instructions are executed. see the software manual for details. figure 1.10. flag register (flg) aaaaaaa aaaaaaa h l b15 b8 b7 b0 r0 (note) aaaaaaa aaaaaaa h l b15 b8 b7 b0 r1 (note) r2 (note) aaaaaaa aaaaaaa b15 b0 r3 (note) aaaaaaa aaaaaaa b15 b0 a0 (note) aaaaaaa aaaaaaa b15 b0 a1 (note) aaaaaaa aaaaaaa b15 b0 fb (note) aaaaaaa aaaaaaa b15 b0 data registers address registers frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 h l program cou n interrupt tabl e register user stack p o interrupt stac k pointer static base register flag register pc intb usp isp sb flg a a aa aa aa aa aa aa aaaaaa aaaaaa aa aa aa aa aa aa aa aa aa aa c d z s b o i u ipl
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer reset 14 figure 1.12. reset sequence reset there are two kinds of resets; hardware and software. in both cases, operation is the same after the reset. (see software reset for details of software resets.) this section explains on hardware resets. when the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level l (0.2v cc max.) for at least 20 cycles. when the reset pin level is then returned to the h level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. figure 1.11 shows the example reset circuit. figure 1.12 shows the reset sequence. figure 1.11. example reset circuit reset v cc 0.8v reset v cc 0v 0v 5v 5v 4.0v example when v cc = 5v . bclk address bclk 24cycles ffffc 16 ffffe 16 content of reset vector x in reset more than 20 cycles are needed (internal clock) (internal address signal)
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer reset 15 figure 1.13. device's internal status after a reset is cleared x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. (1) (0004 16 ) processor mode register 0 (2) (0005 16 ) processor mode register 1 (3) (0006 16 ) system clock control register 0 (4) (0007 16 ) system clock control register 1 (5) (6) (0009 16 ) address match interrupt enable register (7) (000a 16 ) (9) (000f 16 ) watchdog timer control register (11) (0014 16 ) (0015 16 ) (0016 16 ) (12) (13) (21) (22) (23) (004d 16 ) key input interrupt control register (20) (8) protect register (0010 16 ) address match interrupt register 0 (0011 16 ) (0012 16 ) (10) (14) (15) (16) (17) (18) (19) (24) a-d conversion interrupt control register (25) (26) (004e 16 ) (27) (28) (29) (30) uart0 transmit interrupt control register uart0 receive interrupt control register uart1 transmit interrupt control register uart1 receive interrupt control register (31) (32) (33) (34) (35) (36) (37) timer a0 interrupt control register timer x0 interrupt control register timer x1 interrupt control register timer x2 interrupt control register timer b0 interrupt control register timer b1 interrupt control register (38) (39) int0 interrupt control register (40) int1 interrupt control register (41) (0051 16 ) (0052 16 ) (0053 16 ) (0054 16 ) (0055 16 ) (0056 16 ) (0057 16 ) (0058 16 ) (005a 16 ) (005b 16 ) (005d 16 ) (005e 16 ) (0383 16 ) trigger select flag (0384 16 ) up-down flag (0396 16 ) timer a0 mode register (0397 16 ) timer x0 mode register (0398 16 ) timer x1 mode register (039b 16 ) timer b0 mode register (039c 16 ) timer b1 mode register (0399 16 ) timer x2 mode register (0382 16 ) one-shot start flag (03a8 16 ) uart1 transmit/receive control register 0 (03ad 16 ) uart1 transmit/receive control register 1 (03b0 16 ) uart transmit/receive control register 2 (03a0 16 ) uart0 transmit/receive mode register (03a4 16 ) uart0 transmit/receive control register 0 (03a5 16 ) uart0 transmit/receive control register 1 count start flag (0380 16 ) (0381 16 ) clock prescaler reset flag 01001000 00 0 00 0 0 0 0 1 000 000????? 0000 0 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 0 0 00 16 00 16 0 0 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 000 ? 00 000 ? 00 000 ? 0 0 0 0 0 00 00000 00 0000000 0001000 0 0000010 0 0001000 0 0000010 0 00 16 00 16 00 0000 ? 00 0000 ? (03ac 16 ) uart1 transmit/receive mode register address match interrupt register 1 (48) (49) (46) (47) (45) (50) (51) (52) (53) (59) (57) (58) (55) (56) (54) (64) (63) (65) (66) (62) (03d4 16 ) a-d control register 2 (03d6 16 ) a-d control register 0 (03d7 16 ) a-d control register 1 (60) (61) (03e2 16 ) port p0 direction register (03e3 16 ) port p1 direction register (03e6 16 ) port p2 direction register (03e7 16 ) port p3 direction register (03ea 16 ) port p4 direction register (03eb 16 ) port p5 direction register (03ee 16 ) port p6 direction register (03ef 16 ) port p7 direction register (03fc 16 ) pull-up control register 0 (03fd 16 ) pull-up control register 1 (03fe 16 ) port p1 drive capacity control register frame base register (fb) address registers (a0/a1) interrupt table register (intb) user stack pointer (usp) interrupt stack pointer (isp) static base register (sb) flag register (flg) data registers (r0/r1/r2/r3) 00000??? 00 16 00 16 00 16 00 16 00 16 00 16 00 16 0000 16 0000 16 0000 16 00000 16 0000 16 0000 16 0000 16 0000 16 0 0000000 000000 000000 00000 00 0 0 0 (43) (44) (42) (03b4 16 ) flash memory control register 0 (note ) (03b5 16 ) flash memory control register 1 (note) (03b6 16 ) flash command register 00 00 16 0 0 0 0 00 0 0 0 1 0 0 note: this register is only exist in flash memory version.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer bus control 16 software reset writing 1 to bit 3 of the processor mode register 0 (address 0004 16 ) applies a (software) reset to the microcomputer. a software reset has almost the same effect as a hardware reset. the contents of internal ram are preserved. figure 1.14 shows the processor mode register 0 and 1. software reset figure 1.14. processor mode register 0 and 1. processor mode register 0 (note) symbol address when reset pm0 0004 16 xxxx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pm03 reserved bit software reset bit the device is reset when this bit is set to ?? the value of this bit is ??when read. note: set bit 1 of the protect register (address 000a 16 ) to ??when writing new values to this register. processor mode register 1 (note) symbol address when reset pm1 0005 16 00xxxxx0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. when write, set "0". when read, their contents are indeterminate. reserved bit must always be set to ? 0 note: set bit 1 of the protect register (address 000a 16 ) to ??when writing new values to this register. a a a a a a pm17 wait bit 0 : no wait state 1 : wait state inserted a a must always be set to 0 0 nothing is assigned. when write, set "0". when read, their contents are indeterminate. 0 0 0 0 0
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer software wait 17 software wait the wait bit (bit 7) of the processor mode register 1 (address 0005 16 )(note) allows you to insert software wait states for the internal rom/ram areas. if this bit is 0, the bus cycle is executed in one bclk (internal clock) period; if the bit is 1, the bus cycle is executed in two bclk periods. this bit is cleared to 0 after a reset. the sfr area is unaffected by this control bit; it is always accessed in two bclk periods. table 1.2 shows the relationship between software wait states and bus cycles. note: before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000a 16 ) to 1. area wait bit bus cycle 1 2 bclk cycles sfr internal rom/ram 0 1 bclk cycle invalid 2 bclk cycles table 1.2. software waits and bus cycles
clock generating circuit under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 18 figure 1.16. examples of sub-clock table 1.3. main clock and sub-clock generating circuits clock generating circuit the clock generating circuit contains two oscillator circuits that supply the operating clock sources to the cpu and internal peripheral units. example of oscillator circuit figure 1.15 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. figure 1.16 shows some examples of sub- clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. circuit constants in figures 15 and 16 vary with each oscillator used. use the values recommended by the manufacturer of your oscillator. figure 1.15. examples of main clock main clock generating circuit sub clock generating circuit use of clock ? cpus operating clock source ? cpus operating clock source ? internal peripheral units ? timer a/b/xs count clock operating clock source source usable oscillator ceramic or crystal oscillator crystal oscillator pins to connect oscillator x in , x out x cin , x cout oscillation stop/restart function available available oscillator status immediately after reset oscillating stopped other externally derived clock can be input m30201 (built-in feedback resistor) x in x out externally derived clock open vcc vss m30201 (built-in feedback resistor) x in x out r d c in c out (note) note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x in and x out following the instruction. m30201 (built-in feedback resistor) x cin x cout externally derived clock open vcc vss m30201 (built-in feedback resistor) x cin x cout (note) c cin c cout r cd note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x cin and x cout following the instruction.
clock generating circuit under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 19 clock control figure 1.17 shows the block diagram of the clock generating circuit. sub clock cm04 f c32 cm0i : bit i at address 0006 16 cm1i : bit i at address 0007 16 wdci : bit i at address 000f 16 x cin cm10 ?? write signal 1/32 x cout q s r wait instruction x out main clock cm05 f c cm02 f 1 q s r interrupt request level judgment output reset software reset f c cm07=0 cm07=1 f ad aaa aaa divider a d 1/2 1/2 1/2 1/2 cm06=0 cm17,cm16=00 cm06=0 cm17,cm16=01 cm06=0 cm17,cm16=10 cm06=1 cm06=0 cm17,cm16=11 d a details of divider x in f 8 f 32 c b b 1/2 c bclk figure 1.17. clock generating circuit
clock generating circuit under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 20 the following paragraphs describes the clocks generated by the clock generating circuit. (1) main clock the main clock is generated by the main clock oscillation circuit. after a reset, the clock is divided by 8 to bclk. the clock can be stopped using the main clock stop bit (bit 5 at address 0006 16 ). stopping the clock, after switching the operating clock source of cpu to the sub-clock, reduces the power dissipation. after the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the x in -x out drive capacity select bit (bit 5 at address 0007 16 ). reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. this bit changes to 1 when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re- tained. (2) sub-clock the sub-clock is generated by the sub-clock oscillation circuit. no sub-clock is generated after a reset. after oscillation is started using the port xc select bit (bit 4 at address 0006 16 ), the sub-clock can be selected as bclk by using the system clock select bit (bit 7 at address 0006 16 ). however, be sure that the sub-clock oscillation has fully stabilized before switching. after the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the x cin -x cout drive capacity select bit (bit 3 at address 0006 16 ). reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. this bit changes to 1 when shifting to stop mode and at a reset. (3) bclk the bclk is the clock that drives the cpu, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. the bclk is derived by dividing the main clock by 8 after a reset. the main clock division select bit 0(bit 6 at address 0006 16 ) changes to 1 when shifting from high- speed/medium-speed to stop mode and at reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) peripheral function clock (f 1 , f 8 , f 32 , f ad ) the clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. the peripheral function clock is stopped by stopping the main clock or by setting the wait peripheral function clock stop bit (bit 2 at 0006 16 ) to 1 and then executing a wait instruction. (5) f c32 this clock is derived by dividing the sub-clock by 32. it is used for the timer a, timer b and timer x counts. (6) f c this clock has the same frequency as the sub-clock. it is used for bclk and for the watchdog timer.
clock generating circuit under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 21 figure 1.18 shows the system clock control registers 0 and 1. figure 1.18. clock control registers 0 and 1 system clock control register 0 (note 1) symbol address when reset cm0 0006 16 48 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p5 4 0 1 : f c output 1 0 : f 8 output 1 1 : clock divide counter output b1 b0 cm07 cm05 cm04 cm03 cm01 cm02 cm00 cm06 clock output function select bit wait peripheral function clock stop bit 0 : do not stop peripheral function clock in wait mode 1 : stop peripheral function clock in wait mode (note 8) x cin -x cout drive capacity select bit (note 2) 0 : low 1 : high port x c select bit 0 : i/o port 1 : x cin -x cout generation main clock (x in -x out ) stop bit (note 3,4,5) 0 : on 1 : off main clock division select bit 0 (note 7) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (note 6) 0 : x in , x out 1 : x cin , x cout note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: changes to ??when shifting to stop mode and at a reset. note 3: this bit is used to stop the main clock when placing the device in a low-power mode. if you want to operate with x in after exiting from the stop mode, set this bit to ?? when operating with a self-excited oscillator, set the system clock select bit (cm07) to ??before setting this bit to ?? note 4: when inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. note 5: if this bit is set to ?? x out turns ?? the built-in feedback resistor remains being connected, so x in turns pulled up to x out (?? via the feedback resistor. note 6: set port xc select bit (cm04) to ??and stabilize the sub-clock oscillating before setting to this bit from ??to ? . do not write to both bits at the same time. and also, set the main clock stop bit (cm05) to ??and stabilize the main clock oscillating before setting this bit from ??to ?? note 7: this bit changes to ??when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 8: f c32 is not included. system clock control register 1 (note 1) symbol address when reset cm1 0007 16 20 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (note 4) 0 : clock on 1 : all clocks off (stop mode) cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high w r w r cm16 cm17 reserved bit always set to ? reserved bit always set to ? main clock division select bit 1 (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 0 reserved bit always set to ? reserved bit always set to ? 0 0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a note 1: set bit 0 of the protect register (address 000a 16 ) to 1 before writing to this register. note 2: this bit changes to 1 when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 3: can be selected when bit 6 of the system clock control register 0 (address 000616) is 0. if 1, division mode is fix ed at 8. note 4: if this bit is set to 1, x out turns h, and the built-in feedback resistor is cut off. x cin and x cout turn high-impedance state.
clock generating circuit under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 22 clock output the clock output function select bit allows you to choose the clock from f 8 , fc, or a divide-by-n clock that is output from the p5 4 /ck out pin. the clock divide counter is an 8-bit counter whose count source is f 32 , and its divide ratio can be set in the range of 00 16 to ff 16 . figure 1.19 shows a block diagram of clock output. figure 1.19. block diagram of clock output clock source selection reload register (8) low-order 8 bits data bus low-order bits p5 4 f 8 f c 1/2 division n+1 n=00 16 to ff 16 clock divided couter (8) example: when f(x in )=10mhz n=07 16 : approx. 16.5khz n=26 16 : approx. 4.0khz n=4d 16 : approx. 2.0khz n=9b 16 : approx. 1.0khz p5 4 /ck out f 32 address 038e 16
clock generating circuit under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 23 pin states port retains status before wait mode clk out when f c selected does not stop when f 8 , clock devided does not stop when the wait counter output selected peripheral function clock stop bit is 0. when the wait peripheral function clock stop bit is 1,the status immedi- ately prior to entering wait mode is maintained. wait mode when a wait instruction is executed, bclk stops and the microcomputer enters the wait mode. in this mode, oscillation continues but bclk and watchdog timer stop. writing 1 to the wait peripheral function clock stop bit and executing a wait instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. table 1.5 shows the status of the ports in wait mode. wait mode is cancelled by a hardware reset or interrupt. if an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as bclk, the clock that had been selected when the wait instruction was executed. table 1.5. port status during wait mode table 1.4. port status during stop mode wait mode pin states port retains status before stop mode clk out when f c selected h when f 8 , clock devided retains status before stop mode counter output selected stop mode writing 1 to the all-clock stop control bit (bit 0 at address 0007 16 ) stops all oscillation and the microcom- puter enters stop mode. in stop mode, the content of the internal ram is retained provided that v cc remains above 2v. because the oscillation of bclk, f 1 to f 32 , fc, fc 32 , and f ad stops in stop mode, peripheral functions such as the a-d converter and watchdog timer do not function. however, timer a, timer b and timer x operate provided that the event counter mode is set to an external pulse, and uart0 functions provided an external clock is selected. table 1.4 shows the status of the ports in stop mode. stop mode is cancelled by a hardware reset or an interrupt. if an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. if returning by an interrupt, that interrupt routine is executed. when shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 0006 16 ) is set to 1. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
clock generating circuit under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 24 0 1 0 0 0 invalid division by 2 mode 1 0 0 0 0 invalid division by 4 mode invalid invalid 0 1 0 invalid division by 8 mode 1 1 0 0 0 invalid division by 16 mode 0 0 0 0 0 invalid no-division mode invalid invalid 1 invalid 0 1 low-speed mode invalid invalid 1 invalid 1 1 low power dissipation mode status transition of bclk power dissipation can be reduced and low-voltage operation achieved by changing the count source for bclk. table 1.6 shows the operating modes corresponding to the settings of system clock control regis- ters 0 and 1. when reset, the device starts in division by 8 mode. the main clock division select bit 0(bit 6 at address 0006 16 ) changes to 1 when shifting from high-speed/medium-speed to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. the following shows the operational modes of bclk. (1) division by 2 mode the main clock is divided by 2 to obtain the bclk. (2) division by 4 mode the main clock is divided by 4 to obtain the bclk. (3) division by 8 mode the main clock is divided by 8 to obtain the bclk. when reset, the device starts operating from this mode. before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. when going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) division by 16 mode the main clock is divided by 16 to obtain the bclk. (5) no-division mode the main clock is divided by 1 to obtain the bclk. (6) low-speed mode f c is used as bclk. note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. at least 2 to 3 seconds are required after the sub- clock starts. therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) low power dissipation mode f c is the bclk and the main clock is stopped. cm17 cm16 cm07 cm06 cm05 cm04 operating mode of bclk status transition of bclk table 1.6. operating modes dictated by settings of system clock control registers 0 and 1 note : before the count source for bclk can be changed from x in to x cin or vice versa, the clock to which the count source is going to be switched must be oscillating stably. allow a wait time in software for the oscillation to stabilize before switching over the clock.
clock generating circuit under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 25 power saving there are three power save modes. (1) normal operating mode ? high-speed mode in this mode, one main clock cycle forms bclk. the cpu operates on the bclk. the peripheral functions operate on the clocks specified for each respective function. ? medium-speed mode in this mode, the main clock is divided into 2, 4, 8, or 16 to form bclk. the cpu operates on the bclk. the peripheral functions operated on the clocks specified for each respective function. ? low-speed mode in this mode, fc forms bclk. the cpu operates on the fc clock. fc is the clock supplied by the subclock. the peripheral functions operate on the clocks specified for each respective function. ? low power-dissipation mode this mode is selected when the main clock is stopped from low-speed mode. the cpu operates on the fc clock. fc is the clock supplied by the subclock. only the peripheral functions for which the subclock was selected as the count source continue to run. (2) wait mode cpu operation is halted in this mode. the oscillator continues to run. (3) stop mode all oscillators stop in this mode. the cpu and internal peripheral functions all stop. of all 3 power saving modes, power savings are greatest in this mode. figure 1.20 shows the transition between each of the three modes, (1), (2), and (3). power saving
clock generating circuit under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 26 figure 1.20. clock transition transition of stop mode, wait mode transition of normal mode reset medium-speed mode (divided-by-8 mode) interrupt cm10 = ? all oscillators stopped cpu operation stopped medium-speed mode (divided-by-8 mode) bclk : f(x in )/8 cm07 = ?? cm06 = ? low-speed mode high-speed mode main clock is oscillating sub clock is stopped main clock is oscillating sub clock is stopped main clock is stopped sub clock is oscillating main clock is oscillating sub clock is oscillating low power dissipation mode high-speed/medium- speed mode low-speed/low power dissipation mode normal mode stop mode stop mode stop mode all oscillators stopped all oscillators stopped wait mode wait mode wait mode cpu operation stopped cpu operation stopped interrupt wait instruction interrupt wait instruction interrupt wait instruction cm10 = ? interrupt interrupt cm10 = ? bclk : f(x in )/2 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-2 mode) bclk : f(x in )/16 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-4 mode) bclk : f(x in ) cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? bclk : f(x in )/8 medium-speed mode (divided-by-8 mode) cm07 = ? cm06 = ? high-speed mode bclk : f(x in )/2 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-2 mode) bclk : f(x in )/16 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-4 mode) bclk : f(x in ) cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? bclk : f(x cin ) cm07 = ? bclk : f(x cin ) cm07 = ? main clock is oscillating sub clock is oscillating cm07 = ? (note 1, 3) cm07 = ??(note 1) cm06 = ? cm04 = ? cm07 = ? (note 2) cm07 = ??(note 1) cm06 = ??(note 3) cm04 = ? cm07 = ??(note 2) cm05 = ?? cm05 = ? cm05 = ? cm04 = ? cm04 = ? cm06 = ? (notes 1,3) cm06 = ? cm04 = ? cm04 = ? (notes 1, 3) note 1: switch clock after oscillation of main clock is sufficiently stable. note 2: switch clock after oscillation of sub clock is sufficiently stable. note 3: change cm06 after changing cm17 and cm16. note 4: transit in accordance with arrow. (refer to the following for the transition of normal mode.) power saving
clock generating circuit under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 27 protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. figure 1.21 shows the protect register. the values in the processor mode register 0 (address 0004 16 ), processor mode register 1 (address 0005 16 ), system clock control reg- ister 0 (address 0006 16 ), system clock control register 1 (address 0007 16 ) and port p4 direction register (address 03ea 16 ) can only be changed when the respective bit in the protect register is set to 1. there- fore, important outputs can be allocated to port p4. if, after 1 (write-enabled) has been written to the port p4 direction register write-enable bit (bit 2 at address 000a 16 ), a value is written to any address, the bit automatically reverts to 0 (write-inhibited). however, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000a 16 ) and processor mode register 0 and 1 write-enable bit (bit 1 at 000a 16 ) do not automatically return to 0 after a value has been written to an address. the program must therefore be written to return these bits to 0. protect register symbol address when reset prcr 000a 16 xxxxx000 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write-inhibited 1 : write-enabled prc1 prc0 prc2 enables writing to processor mode registers 0 and 1 (addresses 0004 16 and 0005 16 ) function 0 : write-inhibited 1 : write-enabled enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) enables writing to port p4 direction register (address 03ea 16 ) (note ) 0 : write-inhibited 1 : write-enabled w r nothing is assigned. these bits can neither be set nor reset. when read, their contents are indeterminate. note: writing a value to an address after ??is written to this bit returns the bit to ??. other bits do not automatically return to ??and they must therefore be reset by the program. a a a a a a figure 1.21. protect register protection
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 28 special peripheral i/o *1 overview of interrupt type of interrupts figure 1.22 lists the types of interrupts. figure 1.22. classification of interrupts ? maskable interrupt : an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt : an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction ? ? ? y ? ? ? t ? y ? t software hardware interrupt ? y ? t ? y ? t reset ________ dbc watchdog timer single step address matched *1 peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 29 software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. ? undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. ? overflow interrupt an overflow interrupt occurs when executing the into instruction with the overflow flag (o flag) set to 1. the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub ? brk interrupt a brk interrupt occurs when executing the brk instruction. ? int interrupt an int interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the int instruction. software interrupt numbers 0 through 31 are assigned to peripheral i/o interrupts, so executing the int instruction allows executing the same interrupt routine that a peripheral i/o interrupt does. the stack pointer (sp) used for the int interrupt is dependent on which software interrupt number is involved. so far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (u flag) when it accepts an interrupt request. if change the u flag to 0 and select the interrupt stack pointer (isp), and then execute an interrupt sequence. when returning from the interrupt routine, the u flag is returned to the state it was before the acceptance of interrupt request. so far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 30 hardware interrupts hardware interrupts are classified into two types special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are non-maskable interrupts. ? reset reset occurs if an l is input to the reset pin. ? dbc interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. ? watchdog timer interrupt generated by the watchdog timer. ? single-step interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. with the debug flag (d flag) set to 1, a single-step interrupt occurs after one instruction is executed. ? address match interrupt an address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to 1. if an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of built-in peripheral functions. the interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the int instruction uses. peripheral i/o interrupts are maskable interrupts. ? key-input interrupt ___ a key-input interrupt occurs if an l is input to the ki pin. ? a-d conversion interrupt this is an interrupt that the a-d converter generates. ? uart0 and uart1 transmission interrupt these are interrupts that the serial i/o transmission generates. ? uart0 and uart1 reception interrupt these are interrupts that the serial i/o reception generates. ? timer a0 interrupt this is an interrupts that timer a0 generates. ? timer b0 and timer b2 interrupt these are interrupts that timer b generates. ? timer x0 to timer x2 interrupt these are interrupts that timer x generates. ________ ________ ? int0 and int1 interrupt ______ ______ an int interrupt occurs if either a rising edge or a falling edge is input to the int pin.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 31 interrupts and interrupt vector tables if an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. figure 1.23 shows format for specifying interrupt vector addresses. two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. interrupt source vector table addresses remarks address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction overflow fffe0 16 to fffe3 16 interrupt on into instruction brk instruction fffe4 16 to fffe7 16 if the vector is filled with ff 16 , program execution starts from the address shown by the vector in the variable vector table address match fffe8 16 to fffeb 16 there is an address-matching interrupt enable bit single step (note) fffec 16 to fffef 16 do not use watchdog timer ffff0 16 to ffff3 16 ________ dbc (note) ffff4 16 to ffff7 16 do not use - ffff8 16 to ffffb 16 - reset ffffc 16 to fffff 16 table 1.7. interrupt and fixed vector address figure 1.23. format for specifying interrupt vector addresses note: interrupts used for debugging purposes only. aaaaaaaa aaaaaaaa mid address aaaaaaaa aaaaaaaa low address aaaaaaaa aaaaaaaa 0 0 0 0 high address aaaaaaaa aaaaaaaa 0 0 0 0 0 0 0 0 vector address + 0 vector address + 1 vector address + 2 vector address + 3 lsb msb ? fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from fffdc 16 to fffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table 1.7 shows the interrupts assigned to the fixed vector tables and addresses of vector tables.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 32 table 1.8. interrupt causes (variable interrupt vector addresses) software interrupt number interrupt source vector table address address (l) to address (h) remarks cannot be masked by i flag +0 to +3 (note) brk instruction software interrupt number 0 +44 to +47 (note) software interrupt number 11 +48 to +51 (note) software interrupt number 12 +52 to +55 (note) software interrupt number 13 +56 to +59 (note) software interrupt number 14 +68 to +71 (note) software interrupt number 17 +72 to +75 (note) software interrupt number 18 +76 to +79 (note) software interrupt number 19 +80 to +83 (note) software interrupt number 20 +84 to +87 (note) software interrupt number 21 +88 to +91 (note) software interrupt number 22 +92 to +95 (note) software interrupt number 23 +96 to +99 (note) software interrupt number 24 +100 to +103 (note) software interrupt number 25 +104 to +107 (note) software interrupt number 26 +108 to +111 (note) software interrupt number 27 +112 to +115 (note) software interrupt number 28 +116 to +119 (note) software interrupt number 29 +120 to +123 (note) software interrupt number 30 +124 to +127 (note) software interrupt number 31 +128 to +131 (note) software interrupt number 32 +252 to +255 (note) software interrupt number 63 to note : address relative to address in interrupt table register (intb). to key input interrupt a-d uart0 transmit uart0 receive uart1 transmit uart1 receive timer a0 timer x0 timer x1 timer x2 timer b0 timer b1 int0 int1 software interrupt cannot be masked by i flag ? variable vector tables the addresses in the variable vector table can be modified, according to the users settings. indicate the first address using the interrupt table register (intb). the 256-byte area subsequent to the address the intb indicates becomes the area for the variable vector tables. one vector table comprises four bytes. set the first address of the interrupt routine in each vector table. table 1.8 shows the interrupts assigned to the variable vector tables and addresses of vector tables.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 33 interrupt control descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. what is described here does not apply to non-maskable interrupts. enable or disable a maskable interrupt using the interrupt enable flag (i flag), interrupt priority level select bit, and processor interrupt priority level (ipl). whether an interrupt request is present or absent is indi- cated by the interrupt request bit. the interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. also, the interrupt enable flag (i flag) and the ipl are located in the flag register (flg). figure 1.24 shows the interrupt control registers.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 34 figure 1.24. interrupt control register symbol address when reset intiic(i=0, 1) 005d 16 , 005e 16 xx00x000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa ilvl0 ir pol nothing is assigned. when write, set "0". when read, their contents are indeterminate. interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge 1 : selects rising edge always set to 0 ilvl1 ilvl2 note: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). (note) interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa aa aa a a bit name function bit symbol w r symbol address when reset kupic 004d 16 xxxxx000 2 adic 004e 16 xxxxx000 2 sitic(i=0, 1) 0051 16 , 0053 16 xxxxx000 2 siric(i=0, 1) 0052 16 , 0054 16 xxxxx000 2 taiic(i=0) 0055 16 xxxxx000 2 txiic(i=0 to 2) 0056 16 to 0058 16 xxxxx000 2 tbiic(i=0, 1) 005a 16 , 005b 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. when write, set "0". when read, their contents are indeterminate. (note) note: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 35 interrupt enable flag the interrupt enable flag (i flag) controls the enabling and disabling of maskable interrupts. setting this flag to 1 enables all maskable interrupts; setting it to 0 disables all maskable interrupts. this flag is set to 0 after reset. interrupt request bit the interrupt request bit is set to "1" by hardware when an interrupt is requested. after the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. the interrupt request bit can also be set to "0" by software. (do not set this bit to "1"). interrupt priority level select bit and processor interrupt priority level (ipl) set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. when an interrupt request occurs, the interrupt priority level is compared with the ipl. the interrupt is enabled only when the priority level of the interrupt is higher than the ipl. therefore, setting the interrupt priority level to 0 disables the interrupt. table 1.9 shows the settings of interrupt priority levels and table 1.10 shows the interrupt levels enabled, according to the consist of the ipl. the following are conditions under which an interrupt is accepted: interrupt enable flag (i flag) = 1 interrupt request bit = 1 interrupt priority level > ipl the interrupt enable flag (i flag), the interrupt request bit, the interrupt priority select bit, and the ipl are independent, and they are not affected by one another. table 1.10. interrupt levels enabled according to the contents of the ipl table 1.9. settings of interrupt priority levels interrupt priority level select bit interrupt priority level priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high b2 b1 b0 enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 2 ipl 1 ipl 0 ipl
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 36 changing the interrupt control register < program examples > the program examples are described as follow: example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; four nop instructions are required when using hold function. nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. if changing the interrupt control register using an instruction other than the instructions listed hear, and if an interrupt occurs associated with this register during execution of the instruction, there can be instances in which the interrupt request bit is not set. to avoid this problem, use one of the instruc- tions given below to change the register. following instructions: and, or, bclr or bset
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 37 interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. in the interrupt sequence, the processor carries out the following in sequence given: (1) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading address 00000 16 . after this, the corresponding interrupt request bit becomes "0". (2) saves the content of the flag register (flg) as it was immediately before the start of interrupt sequence in the temporary register (note) within the cpu. (3) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer select flag (u flag) to 0 (the u flag, however, does not change if the int instruction, in software interrupt numbers 32 through 63, is executed). (4) saves the content of the temporary register (note) within the cpu in the stack area. (5) saves the content of the program counter (pc) in the stack area. (6) sets the interrupt priority level of the accepted instruction in the ipl. interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. this time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure 1.25 shows the interrupt response time. instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) time from interrupt request is generated to when the instruction then under execution is completed. (b) time in which the instruction sequence is executed. figure 1.25. interrupt response time after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 38 interrupt sources without priority levels 7 value set in the ipl watchdog timer other not changed 0 variation of ipl when interrupt request is accepted if an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. if an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in table 1.12 is set in the ipl. table 1.12. relationship between interrupts without interrupt priority levels and ipl table 1.11. time required for executing the interrupt sequence reset time (a) is dependent on the instruction under execution. thirty cycles is the maximum required for the divx instruction (without wait). time (b) is as shown in table 1.11. ________ note 1: add 2 cycles in the case of a dbc interrupt; add 1 cycle in the case either of an address match interrupt or of a single-step interrupt. note 2: locate an interrupt vector address in an even address, if possible. figure 1.26. time required for executing the interrupt sequence stack pointer (sp) value interrupt vector address 16-bit bus, without wait 8-bit bus, without wait even even odd (note 2) odd (note 2) even odd even odd 18 cycles (note 1) 19 cycles (note 1) 19 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) indeterminate 123456789 1011 12 13 14 15 16 17 18 the indeterminate segment is dependent on the queue buffer. if the queue buffer is ready to take an instruction, a read cycle occurs. indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 16 indeterminate sp-2 sp-4 vec vec+2 pc bclk address bus data bus w r
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 39 saving registers in the interrupt sequence, only the contents of the flag register (flg) and that of the program counter (pc) are saved in the stack area. first, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8 low- order bits of the flg register, 16 bits in total, in the stack area, then saves 16 low-order bits of the program counter. figure 1.27 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. save other necessary registers at the beginning of the interrupt routine using software. using the pushm instruction alone can save all the registers except the stack pointer (sp). figure 1.27. state of stack before and after acceptance of interrupt request address content of previous stack stack area [sp] stack pointer value before interrupt occurs m m ?1 m ?2 m ?3 m ?4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m ?1 m ?2 m ?3 m ?4 address flag register (flg l ) content of previous stack stack area flag register (flg h ) program counter (pc h ) [sp] new stack pointer value content of previous stack m + 1 msb lsb program counter (pc l ) program counter (pc m )
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 40 figure 1.28. operation of saving registers the operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer (note), at the time of acceptance of an interrupt request, is even or odd. if the content of the stack pointer (note) is even, the content of the flag register (flg) and the content of the program counter (pc) are saved, 16 bits at a time. if odd, their contents are saved in two steps, 8 bits at a time. figure 1.28 shows the operation of the saving registers. note: stack pointer indicated by u flag. (2) stack pointer (sp) contains odd number [sp] (odd) [sp] ?1 (even) [sp] ?2(odd) [sp] ?3 (even) [sp] ?4(odd) [sp] ?5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) stack pointer (sp) contains even number [sp] (even) [sp] ?1(odd) [sp] ?2 (even) [sp] ?3(odd) [sp] ?4 (even) [sp] ?5 (odd) note: [sp] denotes the initial value of the stack pointer (sp) when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) saved simultaneously, all 8 bits flag register (flg h ) program counter (pc h ) flag register (flg h ) program counter (pc h )
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 41 returning from an interrupt routine executing the reit instruction at the end of an interrupt routine returns the contents of the flag register (flg) as it was immediately before the start of interrupt sequence and the contents of the program counter (pc), both of which have been saved in the stack area. then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process re- sumes. return the other registers saved by software within the interrupt routine using the popm or similar in- struction before executing the reit instruction. interrupt priority if there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. assign an arbitrary priority to maskable interrupts (peripheral i/o interrupts) using the interrupt priority level select bit. if the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. priorities of the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. figure 1.29 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. interrupt priority level judge circuit this circuit selects the interrupt with the highest priority level when two or more interrupts are generated simultaneously. figure 1.30 shows the interrupt resolution circuit.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 42 figure 1.30. interrupt resolution circuit timer b0 timer x2 timer x0 timer b1 timer x1 uart1 reception uart0 reception a-d conversion timer a0 uart1 transmission uart0 transmission key input interrupt processor interrupt priority level (ipl) interrupt enable flag (i flag) int1 int0 watchdog timer reset dbc interrupt request accepted level 0 (initial value) priority level of each interrupt high low priority of peripheral i/o interrupts (if priority levels are same) address match interrupt request level judgment output figure 1.29. hardware interrupts priorities ________ reset > dbc > watchdog timer > peripheral i/o > single step > address match
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 43 key input interrupt key input interrupt if the direction register of any of p0 0 to p0 7 is set for input and a falling edge is input to that port, a key input interrupt is generated. a key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. figure 1.31 shows the block diagram of the key input interrupt. note that if an l level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. figure 1.31. block diagram of key input interrupt interrupt control circuit key input interrupt control register (address 004d 16 ) key input interrupt request p0 7 /ki 7 p0 6 /ki 6 p0 1 /ki 1 p0 0 /ki 0 port p0 4 -p0 7 pull-up select bit port p0 7 direction register pull-up transistor port p0 7 direction register port p0 6 direction register port p0 1 direction register port p0 0 direction register pull-up transistor pull-up transistor pull-up transistor
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 44 address match interrupt an address match interrupt is generated when the address match interrupt address register contents match the program counter value. two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not affected by the inter- rupt enable flag (i flag) and processor interrupt priority level (ipl). figure 1.32 shows the address match interrupt-related registers. bit name bit symbol symbol address when reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function w r aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 aaaaaaaaaaaaaa aaaaaaaaaaaaaa symbol address when reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 nothing is assigned. when write, set "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 w r address setting register for address match interrupt function values that can be set address match interrupt register i (i = 0, 1) 00000 16 to fffff 16 nothing is assigned. when write, set "0". when read, their contents are indeterminate. 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) aa a aa a aa aa a a address match interrupt figure 1.32. address match interrupt-related registers
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer interrupts 45 precautions for interrupts (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. concerning the first instruction immediately after reset, generating any interrupts is prohibited. (3) external interrupt ________ ? either an l level or an h level of at least 250 ns width is necessary for the signal input to pins int0 ________ and int1 regardless of the cpu operation clock. ________ ________ ? when changing a polarity of pins int0 and int1, the interrupt request bit may become "1". clear the ______ interrupt request bit after changing the polarity. figure 1.33 shows the switching condition of int inter- rupt request. ______ figure 1.33. switching condition of int interrupt request (4) changing interrupt control register see "changing interrupt control register". set the interrupt priority level to level 0 (disable inti interrupt) set the polarity select bit clear the interrupt request bit to ? set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) clear the interrupt enable flag to ? (disable interrupt) set the interrupt enable flag to ? (enable interrupt)
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer watchdog timer 46 write to the watchdog timer start register (address 000e 16 ) reset watchdog timer interrupt request watchdog timer set to ?fff 16 1/128 1/16 ?m07 = 0 ?dc7 = 1 ?m07 = 0 ?dc7 = 0 ?m07 = 1 bclk 1/2 prescaler figure 1.34. block diagram of watchdog timer watchdog timer the watchdog timer has the function of detecting when the program is out of control. the watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the bclk using the prescaler. a watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. when x in is selected for the bclk, bit 7 of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or by 128). when x cin is selected as the bclk, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000f 16 ). when x in is selected in bclk watchdog timer cycle = when x cin is selected in bclk watchdog timer cycle = for example, when bclk is 10mhz and the prescaler division ratio is set to 16, the watchdog timer cycle is approximately 52.4 ms. the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler is initialized only when the microcomputer is reset. after a reset is cancelled, the watchdog timer and prescaler are both stopped. the count is started by writing to the watchdog timer start register (address 000e 16 ). figure 1.34 shows the block diagram of the watchdog timer. figure 1.35 shows the watchdog timer-related registers. prescaler division ratio (16 or 128) x watchdog timer count (32768) bclk prescaler division ratio (2) x watchdog timer count (32768) bclk
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer watchdog timer 47 watchdog timer control register symbol address when reset wdc 000f 16 000xxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 watchdog timer start register symbol address when reset wdts 000e 16 indeterminate w r b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to ?fff 16 regardless of whatever value is written. reserved bit reserved bit must always be set to ? must always be set to ? 0 0 aa aa a aa a aa a a figure 1.35. watchdog timer control and start registers
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer a 48 timer there are six 16-bit timers. these timers can be classified by function into timer a (one), timers b (two) and timers x (three). all these timers function independently. figure 1.36 show the block diagram of timers. figure 1.36. timer block diagram ta0 in tx0 inout tb0 in tb1 in f 1 f 8 f 32 f c32 1/32 f c32 1/8 1/4 f 1 f 8 f 32 x in x cin tx1 inout tx2 inout noise filter noise filter noise filter noise filter noise filter noise filter ?event counter mode ?event counter mode ?event counter mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?pulse width measuring mode ?timer mode ?one-shot mode ?pwm mode ?pulse width measuring mode ?event counter mode ?event counter mode ?event counter mode ?timer mode ?one-shot mode ?pwm mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode timer a0 timer x0 timer x1 timer x2 timer b0 timer b1 timer a0 timer x0 timer x1 timer x2 timer b0 timer b1 clock prescaler reset flag (bit 7 at address 0381 16 ) set to ? reset clock prescaler
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer a 49 timer a figure 1.37 shows the block diagram of timer a. figures 1.38 to 1.40 show the timer a-related registers. use the timer a0 mode register bits 0 and 1 to choose the desired mode. timer a has the four operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer over flow. ? one-shot timer mode: the timer stops counting when the count reaches 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses of a given width. figure 1.38. timer a-related registers (1) figure 1.37. block diagram of timer a count start flag up count/down count always down count except in event counter mode reload register (16) counter (16) low-order 8 bits aaa high-order 8 bits clock source selection timer (gate function) timer one shot pwm f 1 f 8 f 32 external trigger ta0 in tb1 overflow event counter f c32 clock selection tx0 overflow pulse output toggle flip-flop ta0 out data bus low-order bits data bus high-order bits a a up/down flag down count tx2 overflow polarity selection timer a0 mode register symbol address when reset ta0mr 0396 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit aa aa a a aa a aa a aa a aa a aa a aa aa a a aa a
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer a 50 figure 1.39. timer a-related registers (2) timer a0 up/down flag timer a0 two-phase pulse signal processing select bit symbol address when reset udf 0384 16 xxx0xxx0 2 ta0p up/down flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ta0ud 0 : down count 1 : up count this specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled when not using the two-phase pulse signal processing function, set the select bit to ? symbol address when reset tabsr 0380 16 000x0000 2 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa clock devided count start flag timer b1 count start flag timer b0 count start flag timer x2 count start flag timer x1 count start flag timer x0 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting cdcs tb1s tb0s nothing is assigned. when write, set "0". when read, their contents are indeterminate. tx2s tx1s tx0s ta0s symbol address when reset ta0 0387 16 ,0386 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer a0 register (note) w r timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set event counter mode 0000 16 to ffff 16 counts pulses from an external source or timer overflow one-shot timer mode 0000 16 to ffff 16 counts a one shot width pulse width modulation mode (16-bit pwm) functions as a 16-bit pulse width modulator pulse width modulation mode (8-bit pwm) timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 00 16 to ff 16 (high-order addresses) 00 16 to fe 16 (low- order addresses) 0000 16 to fffe 16 note: read and write data in 16-bit units. aa a aa aa a a aa aa a a aa a aa a aa a aa a aa a a aa a aa aa a a a a a a 0 : stops counting 1 : starts counting nothing is assigned. when write, set "0". when read, their contents are indeterminate. nothing is assigned. when write, set "0". when read, their contents are indeterminate.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer a 51 figure 1.40. timer a-related registers (3) symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa a aaaaaaaaaaaaa a aaaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? cpsr w r nothing is assigned. when write, set "0". when read, their contents are indeterminate. ta0tgl symbol address when reset trgsr 0383 16 00 16 timer a0 event/trigger select bit 0 0 : input on ta0 in is selected (note) 0 1 : tb1 overflow is selected 1 0 : tx2 overflow is selected 1 1 : tx0 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on tx0 inout is selected (note) 0 1 : tb1 overflow is selected 1 0 : ta0 overflow is selected 1 1 : tx1 overflow is selected 0 0 : input on tx1 inout is selected (note) 0 1 : tb1 overflow is selected 1 0 : tx0 overflow is selected 1 1 : tx2 overflow is selected 0 0 : input on tx2 inout is selected (note) 0 1 : tb1 overflow is selected 1 0 : tx1 overflow is selected 1 1 : ta0 overflow is selected timer x0 event/trigger select bit timer x1 event/trigger select bit timer x2 event/trigger select bit w r ta0tgh tx0tgl tx0tgh tx1tgl tx1tgh tx2tgl tx2tgh b1 b0 b3 b2 b5 b4 b7 b6 note: set the corresponding port direction register to ??input mode). tx0os tx1os ta0os one-shot start flag symbol address when reset onsf 0382 16 xxxx0000 2 timer a0 one-shot start flag timer x0 one-shot start flag timer x1 one-shot start flag timer x2 one-shot start flag tx2os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. when write, set "0". when read, its content is indeterminate. w r 1 : timer start when read, the value is ? a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer a 52 item specification count source f 1 , f 8 , f 32 , fc 32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing when the timer underflows ta0in pin function programmable i/o port or gate input ta0out pin function programmable i/o port or pulse output read from timer count value can be read out by reading timer a0 register write to timer ? when counting stopped when a value is written to timer a0 register, it is written to both reload register and counter ? when counting in progress when a value is written to timer a0 register, it is written to only reload register (transferred to counter at next reload time) select function ? gate function counting can be started and stopped by the ta0 in pins input signal ? pulse output function each time the timer underflows, the ta0 out pins polarity is reversed (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.13.) figure 1.41 shows the timer a0 mode register in timer mode. table 1.13. specifications of timer mode figure 1.41. timer a0 mode register in timer mode note 1: set the corresponding port direction register to ??(output mode). note 2: the bit can be ??or ?? note 3: set the corresponding port direction register to ??(input mode). timer a0 mode register symbol address when reset ta0mr 0396 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta0 out pin is a normal port pin) 1 : pulse is output (note 1) (ta0 out pin is a pulse output pin) gate function select bit 0 x (note 2) : gate function not available (ta0 in pin is a normal port pin) 1 0 : timer counts only when ta0 in pin is held ??(note 3) 1 1 : timer counts only when ta0 in pin is held ??(note 3) b4 b3 mr2 mr1 mr3 0 (must always be fixed to ??in timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 00 0 aa a aa a aa a aa a aa aa a a aa a aa aa a a aa aa a a
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer a 53 item specification count source ? external signals input to ta0 in pin (effective edge can be selected by software) ? tb1 overflow, tx0 overflow, tx2 overflow count operation ? up count or down count can be selected by external signal or software ? when the timer overflows or underflows, it reloads the reload register con tents before continuing counting (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer overflows or underflows ta0 in pin function programmable i/o port or count source input ta0 out pin function programmable i/o port, pulse output, or up/down count select input read from timer count value can be read out by reading timer a0 register write to timer ? when counting stopped when a value is written to timer a0 register, it is written to both reload register and counter ? when counting in progress when a value is written to timer a0 register, it is written to only reload register (transferred to counter at next reload time) select function ? free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ? pulse output function each time the timer overflows or underflows, the ta0 out pins polarity is reversed note: this does not apply when the free-run function is selected. (2) event counter mode in this mode, the timer counts an external signal or an internal timers overflow. timer a0 can count a single-phase and a two-phase external signal. table 1.14 lists timer specifications when counting a single-phase external signal. figure 1.42 shows the timer a0 mode register in event counter mode. table 1.15 lists timer specifications when counting a two-phase external signal. figure 1.43 shows the timer a0 mode register in event counter mode. table 1.14. timer specifications in event counter mode (when not processing two-phase pulse signal) figure 1.42. timer a0 mode register in event counter mode timer a0 mode register (when not using two-phase pulse signal processing) note 1: set the corresponding port direction register to ??(output mode). note 2: this bit is valid when only counting an external signal. note 3: set the corresponding port direction register to ??(input mode). note 4: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16 ) is set to ??and event/trigger select bits (addresses 0383 16 ) to ?0? symbol address when reset ta0mr 0396 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta0 out pin is a normal port pin) 1 : pulse is output (note 1) (ta0 out pin is a pulse output pin) count polarity select bit (note 2) mr2 mr1 mr3 0 (must always be fixed to ??in event counter mode) tck0 count operation type select bit 01 0 0 : counts external signal's falling edge 1 : counts external signal's rising edge up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 3) 0 : reload type 1 : free-run type bit symbol bit name function rw tck1 tmod1 a a aa aa a aa a aa a aa a aa a aa a aa a aa two-phase pulse operation select bit (note 4) 0 : normal processing operation 1 : multiply-by-4 processing operation
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer a 54 item specification count source ? two-phase pulse signals input to ta0 in or ta0 out pin count operation ? up count or down count can be selected by two-phase pulse signal ? when the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (note) divide ratio ? 1/ (ffff 16 - n + 1) for up count ? 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing timer overflows or underflows ta0 in pin function two-phase pulse input ta0 out pin function two-phase pulse input read from timer count value can be read out by reading timer a0 register write to timer ? when counting stopped when a value is written to timer a0 register, it is written to both reload regis- ter and counter ? when counting in progress when a value is written to timer a0 register, it is written to only reload regis- ter. (transferred to counter at next reload time.) select function ? normal processing operation the timer counts up rising edges or counts down falling edges on the ta0 in pin when input signal on the ta0 out pin is h ? multiply-by-4 processing operation if the phase relationship is such that the ta0 in pin goes h when the input signal on the ta0 out pin is h, the timer counts up rising and falling edges on the ta0 out and ta0 in pins. if the phase relationship is such that the ta0 in pin goes l when the input signal on the ta0 out pin is h, the timer counts down rising and falling edges on the ta0 out and ta0 in pins. note: this does not apply when the free-run function is selected. table 1.15. timer specifications in event counter mode (when processing two-phase pulse signal) ta0 out up count up count up count down count down count down count ta0 in ta0 out ta0 in count up all edges count up all edges count down all edges count down all edges
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer a 55 figure 1.43. timer a0 mode register in event counter mode note: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16 ) is set to ?? also, always be sure to set the event/trigger select bit (addresses 0383 16 ) to ?0? timer a0 mode register (when using two-phase pulse signal processing) symbol address when reset ta0mr 0396 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 0 (must always be ??when using two-phase pulse signal processing) 0 (must always be ??when using two-phase pulse signal processing) mr2 mr1 mr3 0 (must always be ??when using two-phase pulse signal processing) tck1 tck0 01 0 1 (must always be ??when using two-phase pulse signal processing) bit name function w r count operation type select bit two-phase pulse processing operation select bit (note) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation 0 0 1 a a a a a a a a a a a a a a a a a a a a
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer a 56 item specification count source f 1 , f 8 , f 32 , f c32 count operation ? the timer counts down ? when the count reaches 0000 16 , the timer stops counting after reloading a new count ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value count start condition ? an external trigger is input ? the timer overflows ? the one-shot start flag is set (= 1) count stop condition ? a new count is reloaded after the count has reached 0000 16 ? the count start flag is reset (= 0) interrupt request generation timing the count reaches 0000 16 ta0 in pin function programmable i/o port or trigger input ta0 out pin function programmable i/o port or pulse output read from timer when timer a0 register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer a0 register, it is written to both reload register and counter ? when counting in progress when a value is written to timer a0 register, it is written to only reload register (transferred to counter at next reload time) table 1.16. timer specifications in one-shot timer mode figure 1.44. timer a0 mode register in one-shot timer mode (3) one-shot timer mode in this mode, the timer operates only once. (see table 1.16.) when a trigger occurs, the timer starts up and continues operating for a given period. figure 1.44 shows the timer a0 mode register in one-shot timer mode. bit name function bit symbol operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta0 out pin is a normal port pin) 1 : pulse is output (note 1) (ta0 out pin is a pulse output pin) mr2 mr1 mr3 0 (must always be ??in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 0 : one-shot start flag is valid 1 : selected by event/trigger select register trigger select bit external trigger select bit (note 2) 0 : falling edge of ta0 in pin's input signal (note 3) 1 : rising edge of ta0 in pin's input signal (note 3) w r a a a a a a a a a a a a a a a a note 1: set the corresponding port direction register to 1 (output mode). note 2: valid only when the ta0 in pin is selected by the event/trigger select bit (addresses 0383 16 ). if timer overflow is selected, this bit can be 1 or 0. note 3: set the corresponding port direction register to 0 (input mode). timer a0 mode register symbol address when reset ta0mr 0396 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer a 57 (4) pulse width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table 1.17.) in this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. figure 1.45 shows the timer a0 mode register in pulse width modulation mode. figure 1.46 shows the example of how a 16-bit pulse width modulator operates. figure 1.47 shows the example of how an 8-bit pulse width modulator operates. figure 1.45. timer a0 mode register in pulse width modulation mode table 1.17. timer specifications in pulse width modulation mode item specification count source f 1 , f 8 , f 32 , fc 32 count operation ? the timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new count at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs when counting 16-bit pwm ? high level width n / fi n : set value ? cycle time (2 16 -1) / fi fixed 8-bit pwm ? high level width n (m+1) / fi n : values set to timer a0 registers high-order address ? cycle time (2 8 -1) (m+1) / fi m : values set to timer a0 registers low-order address count start condition ? external trigger is input ? the timer overflows ? the count start flag is set (= 1) count stop condition ? the count start flag is reset (= 0) 8 bits pwm ? set value of "h" level width is except ff 16 , 00 16 : pwm pulse goes l ? set value of "h" level width is ff 16 , 00 16 : timing that count value goes to 01 16 16 bits pwm ? set value of "h" level width is except ffff 16 , 0000 16 : pwm pulse goes l ? set value of "h" level width is ffff 16 , 0000 16 : timing that count value goes to 0001 16 ta0 in pin function programmable i/o port or trigger input ta0 out pin function pulse output read from timer when timer a0 register is read, it indicates an indeterminate value write to timer ? when counting stopped :when a value is written to timer a0 register, it is written to both reload register and counter ? when counting in progress : when a value is written to timer a0 register, it is written to only reload register (transferred to counter at next reload time) bit name function bit symbol operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit w r 11 1 1 (must always be ??in pwm mode) 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit (note 1) 0: falling edge of ta0 in pin's input signal (note 2) 1: rising edge of ta0 in pin's input signal (note 2) 0: count start flag is valid 1: selected by event/trigger select register note 1: valid only when the ta0 in pin is selected by the event/trigger select bit (addresses 0383 16 ). if timer overflow is selected, this bit can be ??or ?? note 2: set the corresponding port direction register to ??(input mode). note 3: set the corresponding port direction register to ??(output mode) when the pulse is output. aa aa a a aa a aa a aa a aa a aa a aa a aa a timer a0 mode register symbol address when reset ta0mr 0396 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request generation timing note: when set value of "h" level width is 00 16 or 0000 16 , pulse outputs "l" level and inversion value, ff 16 or ffff 16 is set to timer.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer a 58 figure 1.46. example of how a 16-bit pulse width modulator operates figure 1.47. example of how an 8-bit pulse width modulator operates 1 / f i x (2 ?1) 16 count source ta0 in pin input signal pwm pulse output from ta0 out pin condition : reload register = 0003 16 , when external trigger (rising edge of ta0 in pin input signal) is selected trigger is not generated by this signal ? ? ? ? timer a0 interrupt request bit ? ? cleared to ??when interrupt request is accepted, or cleared by software f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) note: n = 0000 16 to ffff 16 . 1 / f i x n count source (note1) ta0 in pin input signal underflow signal of 8-bit prescaler (note2) pwm pulse output from ta0 out pin ? ? ? ? ? ? ? ? timer a0 interrupt request bit cleared to ??when interrupt request is accepted, or cleaerd by software f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m = 00 16 to ff 16 ; n = 00 16 to ff 16 . aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa condition : reload register high-order 8 bits = 02 16 reload register low-order 8 bits = 02 16 external trigger (falling edge of ta0 in pin input signal) is selected 1 / f i x (m + 1) x (2 e 1) 8 1 / f i x (m + 1) x n 1 / f i x (m + 1)
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer b 59 timer b figure 1.48 shows the block diagram of timer b. figures 1.49 and 1.50 show the timer b-related registers. use the timer bi mode register (i = 0, 1) bits 0 and 1 to choose the desired mode. timer b has three operation modes listed as follows: ? timer mode : the timer counts an internal count source. ? event counter mode : the timer counts pulses from an external source or a timer overflow. ? pulse period/pulse width measuring mode : the timer measures an external signal's pulse period or pulse width. figure 1.48. block diagram of timer b timer bi mode register symbol address when reset tbimr(i = 0, 1) 039b 16 , 039c 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : inhibited b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit (note 1) (note 2) note 1: timer b0. note 2: timer b1. note 3: must set ?0?to operation mode select bit of m30200. a aa a a aa aa a a aa aa a aa a aa a aa a aa a a clock source selection event counter timer pulse period/pulse width measurement reload register (16) low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 f 8 f 32 tbj overflow (j = 1 when i = 0, j = 0 when i = 1) can be selected in only event counter mode count start flag f c32 polarity switching and edge pulse tbi in (i = 0, 1) counter reset circuit counter (16) figure 1.49. timer b-related registers (1)
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer b 60 symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa a aaaaaaaaaaaaa a aaaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? cpsr nothing is assigned. when write, set "0". when read, their contents are indeterminate. a a symbol address when reset tb0 0391 16 , 0390 16 indeterminate tb1 0393 16 , 0392 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (note) w r pulse period / pulse width measurement mode measures a pulse period or width timer mode 0000 16 to ffff 16 counts the timer's period function values that can be set event counter mode 0000 16 to ffff 16 counts external pulses input or a timer overflow note1: read and write data in 16-bit units. a a a a a a symbol address when reset tabsr 0380 16 000x0000 2 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa clock devided count start flag timer b1 count start flag timer b0 count start flag timer x2 count start flag timer x1 count start flag timer x0 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting cdcs tb1s tb0s nothing is assigned. when write, set "0". when read, their contents are indeterminate. tx2s tx1s tx0s ta0s a a a a a a a a a a a a a a a a 0 : stops counting 1 : starts counting figure 1.50. timer b-related registers (2)
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer b 61 item specification count source f 1 , f 8 , f 32 , f c32 count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbi in pin function programmable i/o port read from timer count value is read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.18.) figure 1.51 shows the timer bi mode register in timer mode. table 1.18. timer specifications in timer mode timer bi mode register symbol address when reset tbimr(i=0, 1) 039b 16 to 039c 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be 0 or 1 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 invalid in timer mode. this bit can neither be set nor reset. when read in timer mode, its content is indeterminate. 0 b7 b6 a a a a a a a a a a a a a a a nothing is assigned. when write, set "0". when read, their contents are indeterminate. figure 1.51. timer bi mode register in timer mode
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer b 62 item specification count source ? external signals input to tbi in pin ? effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbi in pin function count source input read from timer count value can be read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) (2) event counter mode in this mode, the timer counts an external signal or an internal timer's overflow. (see table 1.19.) figure 1.52 shows the timer bi mode register in event counter mode. table 1.19. timer specifications in event counter mode figure 1.52. timer bi mode register in event counter mode timer bi mode register symbol address when reset tbimr(i=0, 1) 039b 16 to 039c 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit (note 1) mr1 mr3 invalid in event counter mode. this bit can neither be set nor reset. when read in event counter mode, its content is indeterminate. tck1 tck0 01 0 0 : counts external signal's falling edges 0 1 : counts external signal's rising edges 1 0 : counts external signal's falling and rising edges 1 1 : inhibited b3 b2 note 1: valid only when input from the tbi in pin is selected as the event clock. if timer's overflow is selected, this bit can be 0 or 1. note 2: set the corresponding port direction register to 0 (input mode). invalid in event counter mode. can be 0 or 1. event clock select 0 : input from tbi in pin (note 2) 1 : tbj overflow ( j = 1 when i = 0, j = 0 when i = 1) a a a a a a a a a a a a a a a a a a a nothing is assigned. when write, set "0". when read, their contents are indeterminate.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer b 63 item specification count source f 1 , f 8 , f 32 , f c32 count operation ? up count ? counter value 0000 16 is transferred to reload register at measurement pulse's effective edge and the timer continues counting count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing ? when measurement pulse's effective edge is input (note 1) ? when an overflow occurs. (simultaneously, the timer bi overflow flag changes to 1. the timer bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer bi mode register.) tbi in pin function measurement pulse input read from timer when timer bi register is read, it indicates the reload registers content (measurement result) (note 2) write to timer cannot be written to (3) pulse period/pulse width measurement mode in this mode, the timer measures the pulse period or pulse width of an external signal. (see table 1.20.) figure 1.53 shows the timer bi mode register in pulse period/pulse width measurement mode. figure 1.54 shows the operation timing when measuring a pulse period. figure 1.55 shows the operation timing when measuring a pulse width. table 1.20. timer specifications in pulse period/pulse width measurement mode figure 1.53. timer bi mode register in pulse period/pulse width measurement mode note 1: an interrupt request is not generated when the first effective edge is input after the timer has started counting. note 2: the value read out from the timer bi register is indeterminate until the second effective edge is input after the timer. timer bi mode register symbol address when reset tbimr(i=0 , 1) 039b 16 , 039c 16 00xx0000 2 bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr1 mr3 tck1 tck0 0 1 0 0 : pulse period measurement (interval between measurement pulse's falling edge to falling edge) 0 1 : pulse period measurement (interval between measurement pulse's rising edge to rising edge) 1 0 : pulse width measurement (interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : inhibited function b3 b2 count source select bit timer bi overflow flag ( note) 0 : timer did not overflow 1 : timer has overflowed 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 note : the timer bi overflow flag changes to ??when the count start flag is ??and a value is written to the timer bi mode register. this flag cannot be set to ??by software. a a a a a a a a a a a a a a a a a nothing is assigned. when write, set "0". when read, their contents are indeterminate.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer b 64 count source measurement pulse count start flag timer bi interrupt request bit timing at which counter reaches ?000 16 ? ? transfer (indeterminate value) ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) when measuring measurement pulse time interval from falling edge to falling edge (note 2) cleared to ??when interrupt request is accepted, or cleared by software. transfer (measured value) ? reload register counter transfer timing figure 1.55. operation timing when measuring a pulse width measurement pulse ? count source count start flag timer bi interrupt request bit timing at which counter reaches ?000 16 ? ? transfer (measured value) transfer (measured value) ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 1) transfer (measured value) (note 1) cleared to ??when interrupt request is accepted, or cleared by software. (note 2) transfer (indeterminate value) reload register counter transfer timing figure 1.54. operation timing when measuring a pulse period
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer x 65 timer x figure 1.56 shows the block diagram of timer x. figures 1.57 to 1.59 show the timer x-related registers. use the timer xi mode register bits 0 and 1 to choose the desired mode. timer x has the five operation modes listed as follows: ? timer mode : the timer counts an internal count source. ? event counter mode : the timer counts pulses from an external source or a timer overflow. ? one-shot timer mode : the timer stops counting when the count reaches 0000 16 . ? pulse period/pulse width measuring mode : the timer measures an external signal's pulse period or pulse width. ? pulse width modulation (pwm) mode : the timer outputs pulses of a given width. figure 1.57. timer x-related registers (1) figure 1.56. block diagram of timer x count start flag reload register (16) counter (16) low-order 8 bits aaa aaa high-order 8 bits clock source selection timer (gate function) timer one shot pwm pulse period/pulse width measurement f 1 f 8 f 32 external trigger txi inout (i=0 to 2) tb1 overflow event counter f c32 clock selection pulse output toggle flip-flop data bus low-order bits data bus high-order bits a a polarity switching and edge pulse counter reset circuit *1 = ta0, *2 = tx1 when tx0 *1 = tx0, *2 = tx2 when tx1 *1 = tx1, *2 = ta0 when tx2 *1 *2 timer xi mode register symbol address when reset tximr(i = 0 to 2) 0397 16 to 0399 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode or pulse period/ pulse width measurement mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit aa a aa a aa a aa aa a a aa a aa aa a a aa a aa a
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer x 66 figure 1.58. timer x-related registers (2) symbol address when reset tabsr 0380 16 000x0000 2 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa clock devided count start flag timer b1 count start flag timer b0 count start flag timer x2 count start flag timer x1 count start flag timer x0 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting cdcs tb1s tb0s nothing is assigned. when write, set "0" when read, their contents are indeterminate. tx2s tx1s tx0s ta0s symbol address when reset tx0 0389 16 ,0388 16 indeterminate tx1 038b 16 ,038a 16 indeterminate tx2 038d 16 ,038c 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer xi register (note) w r timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set event counter mode 0000 16 to ffff 16 counts pulses from an external source or timer overflow one-shot timer mode 0000 16 to ffff 16 counts a one shot width pulse width modulation mode (16-bit pwm) functions as a 16-bit pulse width modulator pulse width modulation mode (8-bit pwm) timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 00 16 to ff 16 (high-order addresses) 00 16 to ff 16 (low- order addresses) 0000 16 to fffe 16 note: read and write data in 16-bit units. a aa a aa a aa a a aa aa a aa a a aa aa a aa a a aa aa a aa aa aa aa 0 : stops counting 1 : starts counting pulse period / pulse width measurement mode measures a pulse period or width a a
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer x 67 figure 1.59. timer x-related registers (3) symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa a aaaaaaaaaaaaaa a aaaaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? cpsr w r nothing is assigned. when write, set "0". when read, their contents are indeterminate. ta0tgl symbol address when reset trgsr 0383 16 00 16 timer a0 event/trigger select bit 0 0 : input on ta0 in is selected (note) 0 1 : tb1 overflow is selected 1 0 : tx2 overflow is selected 1 1 : tx0 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on tx0 inout is selected (note) 0 1 : tb1 overflow is selected 1 0 : ta0 overflow is selected 1 1 : tx1 overflow is selected 0 0 : input on tx1 inout is selected (note) 0 1 : tb1 overflow is selected 1 0 : tx0 overflow is selected 1 1 : tx2 overflow is selected 0 0 : input on tx2 inout is selected (note) 0 1 : tb1 overflow is selected 1 0 : tx1 overflow is selected 1 1 : ta0 overflow is selected timer x0 event/trigger select bit timer x1 event/trigger select bit timer x2 event/trigger select bit w r ta0tgh tx0tgl tx0tgh tx1tgl tx1tgh tx2tgl tx2tgh b1 b0 b3 b2 b5 b4 b7 b6 note: set the corresponding port direction register to ??input mode). tx0os tx1os ta0os one-shot start flag symbol address when reset onsf 0382 16 xxxx0000 2 timer a0 one-shot start flag timer x0 one-shot start flag timer x1 one-shot start flag timer x2 one-shot start flag tx2os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. when write, set "0". when read, its content is indeterminate. w r 1 : timer start when read, the value is ? a a aa aa a aa a aa a aa a a aa aa a aa a aa a aa a aa a aa a aa a aa a aa a a aa aa
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer x 68 item specification count source f 1 , f 8 , f 32 , f c32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing when the timer underflows txi inout pin function programmable i/o port, gate input or pulse output read from timer count value can be read out by reading timer xi register write to timer ? when counting stopped when a value is written to timer xi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer xi register, it is written to only reload register (transferred to counter at next reload time) select function ? gate function counting can be started and stopped by the txi inout pins input signal ? pulse output function each time the timer underflows, the txi inout pins polarity is reversed (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.21.) figure 1.60 shows the timer xi mode register in timer mode. table 1.21. specifications of timer mode figure 1.60. timer xi mode register in timer mode note 1: set the corresponding port direction register to ??(output mode). gate function cannot be selected when pulse output function is selected. note 2: the bit can be ??or ?? note 3: set the corresponding port direction register to ??(input mode). pulse output function cannot be selected when gate function is selected. timer xi mode register symbol address when reset tximr(i = 0 to 2) 0397 16 to 0399 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (txi inout pin is a normal port pin) 1 : pulse is output (note 1) (txi inout pin is a pulse output pin) gate function select bit 0 x (note 2) : gate function not available (txi inout pin is a normal port pin) 1 0 : timer counts only when txi inout pin is held ??(note 3) 1 1 : timer counts only when txi inout pin is held ??(note 3) b4 b3 mr2 mr1 mr3 0 (must always be fixed to ??in timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 00 0 aa a aa a aa a aa a aa a aa a aa a aa a
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer x 69 item specification count source ? external signals input to txi inout pin (effective edge can be selected by software) ? tb1 overflow, ta0 overflow, txi overflow count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting (note) divide ratio 1/ (n + 1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows txi inout pin function programmable i/o port, count source input or pulse output read from timer count value can be read out by reading timer xi register write to timer ? when counting stopped when a value is written to timer xi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer xi register, it is written to only reload register (transferred to counter at next reload time) select function ? free-run count function even when the timer underflows, the reload register content is not reloaded to it ? pulse output function each time the timer underflows, the txi inout pins polarity is reversed note: this does not apply when the free-run function is selected. (2) event counter mode in this mode, the timer counts an external signal or an internal timers overflow. (see table 1.22.) figure 1.61 shows the timer xi mode register in event counter mode. table 1.22. timer specifications in event counter mode (when not processing two-phase pulse signal) figure 1.61. timer xi mode register in event counter mode timer xi mode register note 1: count source is selected by event/trigger select bit(address 0383 16 ) in event counter mode. note 2: set the corresponding port direction register to ??(output mode). txi inout pin input is not selected as count source when pulse output function is selected. note 3: this bit is valid when only counting an external signal. symbol address when reset tximr(i = 0 to 2) 0397 16 to 0399 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode (note 1) b1 b0 tmod0 mr0 pulse output function select bit 0 : pulse is not output (txi inout pin is a normal port pin) 1 : pulse is output (note 2) (txi inout pin is a pulse output pin) count polarity select bit (note 3) mr2 mr1 mr3 0 (must always be fixed to ??in event counter mode) tck0 count operation type select bit 01 0 0 : counts external signal's falling edge 1 : counts external signal's rising edge 0 : reload type 1 : free-run type bit symbol bit name function rw tck1 tmod1 a aa a aa a aa a aa a aa a aa a aa a aa invalid in event counter mode. can be 0 or 1. invalid in event counter mode. can be 0 or 1.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer x 70 item specification count source f 1 , f 8 , f 32 , f c32 count operation ? the timer counts down ? when the count reaches 0000 16 , the timer stops counting after reloading a new count ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value count start condition ? an external trigger is input ? the timer overflows ? the one-shot start flag is set (= 1) count stop condition ? a new count is reloaded after the count has reached 0000 16 ? the count start flag is reset (= 0) interrupt request generation timing the count reaches 0000 16 txi inout pin function programmable i/o port, trigger input or pulse output read from timer when timer xi register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer xi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer xi register, it is written to only reload register (transferred to counter at next reload time) table 1.23. timer specifications in one-shot timer mode figure 1.62. timer xi mode register in one-shot timer mode (3) one-shot timer mode in this mode, the timer operates only once. (see table 1.23.) when a trigger occurs, the timer starts up and continues operating for a given period. figure 1.62 shows the timer xi mode register in one-shot timer mode. bit name function bit symbol operation mode select bit 1 0 : one-shot timer mode or pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (txi inoout pin is a normal port pin) 1 : pulse is output (note 1) (txi inoout pin is a pulse output pin) mr2 mr1 mr3 0 (must always be ??in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 0 : one-shot start flag is valid 1 : selected by event/trigger select register (note 4) trigger select bit external trigger select bit (note 2) 0 : falling edge of txi inoout pin's input signal (note 3) 1 : rising edge of txi inoout pin's input signal (note 3) w r a aa a a aa aa a aa a a aa aa a aa a aa a aa a aa note 1: set the corresponding port direction register to 1 (output mode). external trigger cannot be selected as count start condition when pulse output function is selected. note 2: valid only when the txi inout pin is selected by the event/trigger select bit (addresses 0383 16 ). if timer overflow is selected, this bit can be 1 or 0. note 3: set the corresponding port direction register to 0 (input mode). note 4: pulse output function cannot be selected when txi inout pin is selected by the event/trigger select bit (addresses 0383 16 ). timer xi mode register symbol address when reset tximr(i = 0 to 2) 0397 16 to 0399 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer x 71 item specification count source f 1 , f 8 , f 32 , f c32 count operation ? up count ? counter value 0000 16 is transferred to reload register at measurement pulse's effective edge and the timer continues counting count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing ? when measurement pulse's effective edge is input (note 1) ? when an overflow occurs. (simultaneously, the timer xi overflow flag changes to 1. the timer xi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer xi mode register.) txi inout pin function measurement pulse input read from timer when timer xi register is read, it indicates the reload registers content (measurement result) (note 2) write to timer cannot be written to (4) pulse period/pulse width measurement mode in this mode, the timer measures the pulse period or pulse width of an external signal. (see table 1.24.) figure 1.63 shows the timer xi mode register in pulse period/pulse width measurement mode. figure 1.64 shows the operation timing when measuring a pulse period. figure 1.65 shows the operation timing when measuring a pulse width. table 1.24. timer specifications in pulse period/pulse width measurement mode figure 1.63. timer xi mode register in pulse period/pulse width measurement mode note 1: an interrupt request is not generated when the first effective edge is input after the timer has started counting. note 2: the value read out from the timer xi register is indeterminate until the second effective edge is input after the timer. bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr1 mr3 tck1 tck0 0 1 0 0 : pulse period measurement (interval between measurement pulse's falling edge to falling edge) 0 1 : pulse period measurement (interval between measurement pulse's rising edge to rising edge) 1 0 : pulse width measurement (interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : inhibited function b3 b2 count source select bit timer xi overflow flag (note) 0 : timer did not overflow 1 : timer has overflowed 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 note: the timer xi overflow flag changes to ??when the count start flag is ??and a value is written to the timer xi mode register. this flag cannot be set to ??by software. aa a aa a aa a aa a aa a aa a aa timer xi mode register symbol address when reset tximr(i = 0 to 2) 0397 16 to 0399 16 00 2 1 0 : one-shot timer mode or pulse period / pulse width measurement mode mr 2 1 (must always be 1 in pulse period / pulse width measurement mode) aa a 1
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer x 72 figure 1.65. operation timing when measuring a pulse width figure 1.64. operation timing when measuring a pulse period count source measurement pulse count start flag timer xi interrupt request bit timing at which counter reaches ?000 16 ? ? transfer (indeterminate value) ? ? ? timer xi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) when measuring measurement pulse time interval from falling edge to falling edge (note 2) cleared to ??when interrupt request is accepted, or cleared by software. transfer (measured value) ? reload register counter transfer timing measurement pulse ? count source count start flag timer xi interrupt request bit timing at which counter reaches ?000 16 ? ? transfer (measured value) transfer (measured value) ? ? ? timer xi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 1) transfer (measured value) (note 1) cleared to ??when interrupt request is accepted, or cleared by software. (note 2) transfer (indeterminate value) reload register counter transfer timing
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer x 73 item specification f 1 , f 8 , f 32 , f c32 ? down counts (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new count at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs when counting ? "h" level width n / fi n : set value ? cycle time (2 16 -1) / fi fixed ? "h" level width n (m+1)/ fi n:values set to timer xi registers high-order address ? cycle time (2 8 -1) (m+1) / fi m : values set to timer xi registers low-order address ? the timer overflows ? the count start flag is set (= 1) ? the count start flag is reset (= 0) ? set value of "h" level width is except ff 16 , 00 16 : pwm pulse goes l ? set value of "h" level width is ff 16 , 00 16 : timing that count value goes to 01 16 ? set value of "h" level width is except ffff 16 , 0000 16 : pwm pulse goes l ? set value of "h" level width is ffff 16 , 0000 16 : timing that count value goes to 0001 16 pulse output when timer xi register is read, it indicates an indeterminate value ? when counting stopped when a value is written to timer xi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer xi register, it is written to only reload register (transferred to counter at next reload time) (5) pulse width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table 1.25.) in this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. figure 1.66 shows the timer xi mode register in pulse width modulation mode. figure 1.67 shows the example of how a 16-bit pulse width modulator operates. figure 1.68 shows the example of how an 8-bit pulse width modulator operates. figure 1.66. timer xi mode register in pulse width modulation mode table 1.25. timer specifications in pulse width modulation mode bit name function bit symbol operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit w r 11 1 1 (must always be ??in pwm mode) 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit 0: count start flag is valid 1: selected by event/trigger select register note 1: txi inout pin inout cannot be selected by the event/trigger select bit(addresses 0383 16 ). note 2: set the corresponding port direction register to ??(output mode). a a a a a a a a a a a a a a a a a a a a timer xi mode register symbol address when reset tximr(i = 0 to 2) 0397 16 to 0399 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 invalid in pwm mode. can be 0 or 1. (note 1) count source count operation 16-bit pwm 8-bit pwm count start condition count stop condition 8 bits pwm 16 bits pwm txi inout pin function read from timer write to timer interrupt request generation timing note: when set value of "h" level width is 00 16 or 0000 16 , pulse outputs "l" level and inversion value, ff 16 or ffff 16 is set to timer.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer timer x 74 figure 1.67. example of how a 16-bit pulse width modulator operates figure 1.68. example of how an 8-bit pulse width modulator operates 1 / f i x (2 ?1) 16 count source trigger signal pwm pulse output from txi inout pin condition : reload register = 0003 16 , when trigger (timer overflow) is selected trigger is not generated by this signal ? ? ? ? timer xi interrupt request bit ? ? cleared to ??when interrupt request is accepted, or cleared by software f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) note1: n = 0000 16 to ffff 16 . 1 / f i x n count source (note1) trigger signal underflow signal of 8-bit prescaler (note2) pwm pulse output from txi inout pin ? ? ? ? ? ? ? ? timer xi interrupt request bit cleared to ??when interrupt request is accepted, or cleaerd by software f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m = 00 16 to ff 16 ; n = 00 16 to ff 16 . aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa condition : reload register high-order 8 bits = 02 16 reload register low-order 8 bits = 02 16 trigger (timer overflow) is selected 1 / f i x (m + 1) x (2 e 1) 8 1 / f i x (m + 1) x n 1 / f i x (m + 1)
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer serial i/o 75 figure 1.69. block diagram of uarti (i = 0, 1) serial i/o serial i/o is configured as two channels: uart0 and uart1. uart0 and uart1 each have an exclusive timer to generate a transfer clock, so they operate indepen- dently of each other. figure 1.69 shows the block diagram of uart0 and uart1. figure 1.70 shows the block diagram of the transmit/receive unit. uart0 has two operation modes: a clock synchronous serial i/o mode and a clock asynchronous serial i/ o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 03a0 16 and 03a8 16 ) determine whether uart0 is used as a clock synchronous serial i/o or as a uart. uart1 is used as a uart only. figures 1.71 through 1.73 show the registers related to uarti. rxd 0 1 / (m+1) 1/2 bit rate generator clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 0 clock source selection f 1 f 8 f 32 reception control circuit transmission control circuit internal external txd 0 transmit/ receive unit rxd 1 1 / (n+1) bit rate generator receive clock transmit clock clock source selection f 1 f 8 f 32 reception control circuit transmission control circuit txd 1 (uart1) (uart0) clk polarity reversing circuit transmit/ receive unit 1/16 1/16 f c 1/16 1/16 m : values set to uart0 bit rate generator (brg0) n : values set to uart1 bit rate generator (brg1) clock output pin select switch clks f c
serial i/o 76 under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer figure 1.70. block diagram of transmit/receive unit sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive register 2sp 1sp par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxdi clock synchronous type uart (8 bits) uart (9 bits) data bus low-order bits msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par ? data bus high-order bits note: uart1 cannot be used in clock synchronous serial i/o.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer serial i/o 77 figure 1.71. serial i/o-related registers (1) b7 uarti bit rate generator b0 symbol address when reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate function assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set w r a b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmit data nothing is assigned. when write, set "0". when read, their contents are indeterminate. symbol address when reset u0tb 03a3 16 , 03a2 16 indeterminate u1tb 03ab 16 , 03aa 16 indeterminate w r a (b15) symbol address when reset u0rb 03a7 16 , 03a6 16 indeterminate u1rb 03af 16 , 03ae 16 indeterminate b7 b0 (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note: bits 15 through 12 are set to 0 when the receive enable bit is set to 0. (bit 15 is set to 0 when bits 14 to 12 all are set to 0.) bits 14 and 13 are also set to 0 when the lower byte of the uarti receive buffer register (addresses 03a6 16 , and 03ae 16 ) is read out. invalid invalid invalid oer fer per sum overrun error flag (note) framing error flag (note) parity error flag (note) error sum flag (note) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found nothing is assigned. when write, set "0". when read, the value of these bits is 0. receive data w r receive data a a a a a a a
serial i/o 78 under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer figure 1.72. serial i/o-related registers (2) uarti transmit/receive mode register symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit (note 1) smd2 internal/external clock select bit (note 2) stps pry prye slep parity enable bit 0 : internal clock 1 : external clock stop bit length select bit odd/even parity select bit sleep select bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = ? 0 : odd parity 1 : even parity invalid invalid must always be ? function (during uart mode) function (during clock synchronous serial i/o mode) a a a a a a a a a a a a a a a a a a a a a a uarti transmit/receive control register 0 symbol address when reset uic0(i=0,1) 03a4 16 , 03ac 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (note) (during clock synchronous serial i/o mode) txept clk1 clk0 nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit data output select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : fc is selected b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : fc is selected b1 b0 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be 0 bit name bit symbol must always be 0 note: uart1 cannot be used in clock synchronous serial i/o. a aa a aa a a aa aa a a aa a aa a aa a aa note 1: uart1 cannot be used in clock synchronous serial i/o. note 2: uart1 can use only internal clock. must set this bit to 1. set this bit to 0. set this bit to 1. 1 0
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer serial i/o 79 figure 1.73. serial i/o-related registers (3) uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 03a5 16 , 03ad 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function (during uart mode) function (note 1) (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit (note 2) receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register nothing is assigned. when write, set "0". when read, the value of these bits is ?? note 1: uart1 cannot be used in clock synchronous serial i/o. note 2: when using multiple pins to output the transfer clock, the following requirements must be met: ?uart0 internal/external clock select bit (bit 3 at address 03a0 16 ) = ?? uart transmit/receive control register 2 symbol address when reset ucon 03b0 16 xx000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function (during uart mode) function (during clock synchronous serial i/o mode) clkmd0 clkmd1 uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable set this bit to ?? clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : normal mode (clk output is clk0 only) 1 : transfer clock output from multiple pins function selected nothing is assigned. when write, set "0". when read, its content is indeterminate. 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) must always be ? u0irs u1irs u0rrm invalid invalid clk/clks select bit 1 (note 2) valid when bit 5 = ?? 0 : clock output to clk1 1 : clock output to clks1 note 1: uart1 cannot be used in clock synchronous serial i/o. note 2: if you are using clock asynchronous serial i/o mode, you can enable 'receive enable bit' when rxd port input is ?? if rxd port input is ??and you have enabled 'receive enable bit' , then receive operation starts immediately. w r aa a aa aa aa a a aa w r aa aa a a aa a aa a aa a aa a aa a set this bit to 0.
clock synchronous serial i/o mode 80 under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. (see table 1.26.) figure 1.65 shows the uart0 transmit/receive mode register. table 1.26. specifications of clock synchronous serial i/o mode specification ? transfer data length: 8 bits ? when internal clock is selected (bit 3 at address 03a0 16 = 0) : fi/ 2(n+1) (note 1) fi = f 1 , f 8 , f 32 , fc ? when external clock is selected (bit 3 at address 03a0 16 = 1) : input from clk0 pin ? to start transmission, the following requirements must be met: _ transmit enable bit (bit 0 at address 03a5 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clk0 polarity select bit (bit 6 at address 03a4 16 ) = 0: clk0 input level = h _ clk0 polarity select bit (bit 6 at address 03a4 16 ) = 1: clk0 input level = l ? to start reception, the following requirements must be met: _ receive enable bit (bit 2 at address 03a5 16 ) = 1 _ transmit enable bit (bit 0 at address 03a5 16 ) = 1 _ transmit buffer empty flag (bit 1 at address 03a5 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clk0 polarity select bit (bit 6 at address 03a4 16 ) = 0: clk0 input level = h _ clk0 polarity select bit (bit 6 at address 03a4 16 ) = 1: clk0 input level = l ? when transmitting _ transmit interrupt cause select bit (bit 0 at address 03b0 16 ) = 0: interrupts re- quested when data transfer from uart0 transfer buffer register to uart0 transmit register is completed _ transmit interrupt cause select bit (bit 0 at address 03b0 16 ) = 1: interrupts re- quested when data transmission from uart0 transfer register is completed ? when receiving _ interrupts requested when data transfer from uart0 receive register to uart0 receive buffer register is completed ? overrun error (note 2) this error occurs when the next data is ready before contents of uart0 receive buffer register are read out ? clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the trans- fer clock can be selected ? lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register ? transfer clock output from multiple pins selection uart0 transfer clock can be chosen by software to be output from one of the two pins set item transfer data format transfer clock transmission start condition reception start conditio interrupt request generation timing error detection select function note 1: n denotes the value 00 16 to ff 16 that is set to the uart bit rate generator. note 2: if an overrun error occurs, the uart0 receive buffer will have the next data written in. note also that the uart0 receive interrupt request bit is not set to 1.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 81 figure 1.74. uart0 transmit/receive mode register in clock synchronous serial i/o mode symbol address when reset u0mr 03a0 16 00 16 ckdir uart0 transmit/receive mode registers internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 (must always be ??in clock synchronous serial i/o mode) 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode a a a a a a a a a a a a a a a a a a a a table 1.27 lists the functions of the input/output pins during clock synchronous serial i/o mode. note that for a period from when the uart0 operation mode is selected to when transfer starts, the txd0 pin outputs a h. (if the n-channel open-drain is selected, this pin is in floating state.) table 1.27. input/output pin functions in clock synchronous serial i/o mode pin name function method of selection txd0 (p5 0 ) serial data output serial data input transfer clock output transfer clock input port p5 0 direction register (bit 0 at address 03eb 16 )= ?? (outputs dummy data when performing reception only) rxd0 (p5 1 ) clk0 (p5 2 ) internal/external clock select bit (bit 3 at address 03a0 16 ) = ? internal/external clock select bit (bit 3 at address 03a0 16 ) = ? port p5 2 direction register (bit 2 at address 03eb 16 ) = ? port p5 1 direction register (bit 1 at address 03eb 16 )= ?? (can be used as an input port when performing transmission only)
clock synchronous serial i/o mode 82 under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer figure 1.75. typical transmit/receive timings in clock synchronous serial i/o mode ? example of transmit timing (when internal clock is selected) ? example of receive timing (when external clock is selected) tc = t clk = 2(n + 1) / fi fi: frequency of brg0 count source (f 1 , f 8 , f 32 , fc) n: value set to brg0 transfer clock transmit enable bit (te) transmit buffer empty flag (tl) clk0 txd0 transmit register empty flag (txept) ? ? ? ? ? ? the above timing applies to the following settings: ?internal clock is selected. ?clk polarity select bit = ?? ?transmit interrupt cause select bit = ?? transmit interrupt request bit (ir) ? ? 1 / f ext dummy data is set in uart0 transmit buffer register transmit enable bit (te) transmit buffer empty flag (tl) clk0 rxd0 receive complete flag (rl) ? ? ? ? ? ? receive enable bit (re) ? ? receive data is taken in transferred from uart0 transmit buffer register to uart0 transmit register read out from uart0 receive buffer register the above timing applies to the following settings: ?external clock is selected. ?clk polarity select bit = ?? f ext : frequency of external clock transferred from uart0 receive register to uart0 receive buffer register receive interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 shown in ( ) are bit symbols. meet the following conditions are met when the clk input before data reception = ? ?transmit enable bit ? ?receive enable bit ? ?dummy data write to uart0 transmit buffer register shown in ( ) are bit symbols. cleared to ??when interrupt request is accepted, or cleared by software tc t clk stopped pulsing because transfer enable bit = ? data is set in uart0 transmit buffer register transferred from uart0 transmit buffer register to uart0 transmit register cleared to ??when interrupt request is accepted, or cleared by software d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 83 (a) polarity select function as shown in figure 1.76, the clk polarity select bit (bit 6 at addresses 03a4 16 ) allows selection of the polarity of the transfer clock. figure 1.76. polarity of transfer clock (b) lsb first/msb first select function as shown in figure 1.77, when the transfer format select bit (bit 7 at addresses 03a4 16 ) = 0, the transfer format is lsb first; when the bit = 1, the transfer format is msb first. figure 1.77. transfer format lsb first ?when transfer format select bit = ? d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d 0 r x d 0 clk 0 ?when transfer format select bit = ? d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d 0 r x d 0 clk 0 msb first note: this applies when the clk polarity select bit = ?? ?when clk polarity select bit = ? note 2: the clk0 pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d 0 r x d 0 clk 0 ?when clk polarity select bit = ? note 1: the clk0 pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d 0 r x d 0 clk 0
clock synchronous serial i/o mode 84 under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer (c) transfer clock output from multiple pins function this function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the clk and clks select bit (bits 4 and 5 at address 03b0 16 ). (see figure 1.78.) the multiple pins function is valid only when the internal clock is selected for uart0. figure 1.78. the transfer clock output from the multiple pins function usage (d) continuous receive mode if the continuous receive mode enable bit (bits 2 and 3 at address 03b0 16 ) is set to 1, the unit is placed in continuous receive mode. in this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. microcomputer t x d 0 (p5 0 ) clks (p5 3 ) clk 0 (p5 2 ) in clk in clk note: this applies when the internal clock is selected and transmission is performed only in clock synchronous serial i/o mode.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 85 item specification ? character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected ? start bit: 1 bit ? parity bit: odd, even, or nothing as selected ? stop bit: 1 bit or 2 bits as selected ? when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 = 0) : fi/ 16 (n+1) (note 1) fi = f 1 , f 8 , f 32 , f c ? when external clock is selected (bit 3 at addresses 03a0 16 =1) : f ext /16(n+1) (note 1) (note 2) ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 ) = 1 - transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 ) = 0 ? to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 ) = 1 - start bit detection ? when transmitting - transmit interrupt cause select bits (bits 0,1 at address 03b0 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bits 0, 1 at address 03b0 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed ? overrun error (note 3) this error occurs when the next data is ready before contents of uarti receive buffer register are read out ? framing error this error occurs when the number of stop bits set is not detected ? parity error this error occurs when if parity is enabled, the number of 1s in parity and character bits does not match the number of 1s set ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered ? sleep mode selection this mode is used to transfer data to and from one of multiple slave micro- computers (2) clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. (see table 1.28.) figure 1.79 shows the uarti transmit/receive mode register. table 1.28. specifications of uart mode note 1: n denotes the value 00 16 to ff 16 that is set to the uart bit rate generator. note 2: f ext is input from the clk0 pin. since uart1 does not have this pin, cannot select external clock. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. transfer data format transfer clock transmission start condition reception start condi- tion interrupt request gen- eration timing error detection select function
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 86 figure 1.79. uarti transmit/receive mode register in uart mode symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit / receive mode registers internal / external clock select bit (note) stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit sleep select bit a a a a a a a a a a a a a a a a a a a a a a note: uart1 can use only internal clock. must set this bit to 1. table 1.29 lists the functions of the input/output pins during uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n- channel open-drain is selected, this pin is in floating state.) table 1.29. input/output pin functions in uart mode pin name function method of selection txdi (p5 0 , p4 0 ) serial data output serial data input programmable i/o port transfer clock input rxdi (p5 1 , p4 2 ) clk0 (p5 2 ) internal/external clock select bit (bit 3 at address 03a0 16 ) = ? internal/external clock select bit (bit 3 at address 03a0 16 ) = ?? port p5 1 and p4 2 direction register (bit 1 at address 03eb 16 , bit 2 at address 03ea 16 )= ?? (can be used as an input port when performing transmission only) port p5 1 and p4 2 direction register (bit 0 at address 03eb 16 , bit 0 at address 03ea 16 )= ?? (can be used as an input port when performing reception only)
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 87 ? example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ? example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) figure 1.80. typical transmit timings in uart mode transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) start bit parity bit txdi the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?transmit interrupt cause select bit = ?? ? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 , f c ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? cleared to ??when interrupt request is accepted, or cleared by software transmit enable bit(te) transmit buffer empty flag(ti) txdi transmit register empty flag (txept) ? ? ? ? ? ? the above timing applies to the following settings : ?parity is disabled. ?two stop bits. ?transmit interrupt cause select bit = ?? transfer clock tc tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? shown in ( ) are bit symbols. shown in ( ) are bit symbols. tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st p sp d 0 d 1 st stopped pulsing because transmit enable bit = ? stop bit transferred from uarti transmit buffer register to uarti transmit register start bit data is set in uarti transmit buffer register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp transferred from uarti transmit buffer register to uarti transmit register stop bit stop bit data is set in uarti transmit buffer register. ? sp cleared to ??when interrupt request is accepted, or cleared by software
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 88 ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) figure 1.81. typical receive timing in uart mode (a) sleep mode this mode is used to transfer data between specific microcomputers among multiple microcomputers connected using uarti. the sleep mode is selected when the sleep select bit (bit 7 at addresses 03a0 16 , 03a8 16 ) is set to 1 during reception. in this mode, the unit performs receive operation when the msb of the received data = 1 and does not perform receive operation when the msb = 0. d 0 start bit sampled ? receive data taken in brgi count source receive enable bit rxdi transfer clock receive complete flag stop bit ? ? ? ? the above timing applies to the following settings : ?arity is disabled. ?ne stop bit. receive interrupt request bit ? ? transferred from uarti receive register to uarti receive buffer register reception triggered when transfer clock is generated by falling edge of start bit d 7 d 1 cleared to ??when interrupt request is accepted, or cleared by software
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer a-d converter 89 item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating clock f ad (note 2) v cc = 5v f ad , divide-by-2 of f ad , divide-by-4 of f ad , f ad =f(x in ) v cc = 3v divide-by-2 of f ad , divide-by-4 of f ad , f ad =f(x in ) resolution 8-bit or 10-bit (selectable) absolute precision v cc = 5v ? without sample and hold function 3lsb ? with sample and hold function (8-bit resolution) 2lsb ? with sample and hold function (10-bit resolution) 3lsb v cc = 3v ? without sample and hold function (8-bit resolution) 2lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 8 pins (an 0 to an 7 ) + 5 pins (an 50 to an 54 ) a-d conversion start condition ? software trigger a-d conversion starts when the a-d conversion start flag changes to 1 conversion speed per pin ? without sample and hold function 8-bit resolution: 49 f ad cycles , 10-bit resolution: 59 f ad cycles ? with sample and hold function 8-bit resolution: 28 f ad cycles , 10-bit resolution: 33 f ad cycles a-d converter the a-d converter consists of one 10-bit successive approximation a-d converter circuit with a capacitive coupling amplifier. pins p6 0 to p6 7 , and p5 0 to p5 4 also function as the analog signal input pins. the direction registers of these pins for a-d conversion must therefore be set to input. the vref connect bit (bit 5 at address 03d7 16 ) can be used to isolate the resistance ladder of the a-d converter from the reference voltage input pin (v ref ) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from v ref , reducing the power dissipation. when using the a-d converter, start a-d conversion only after setting bit 5 of 03d7 16 to connect v ref . the result of a-d conversion is stored in the a-d registers of the selected pins. when set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. when set to 8-bit precision, the low 8 bits are stored in the even addresses. table 1.30 shows the performance of the a-d converter. figure 1.82 shows the block diagram of the a-d converter, and figures 1.83 and 1.84 show the a-d converter-related registers. note 1: does not depend on use of sample and hold function. note 2: without sample and hold function, set the f ad frequency to 250khz min. with the sample and hold function, set the f ad frequency to 1mhz min. table 1.30. performance of a-d converter
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer a-d converter 90 figure 1.82. block diagram of a-d converter 1/2 f ad 1/2 f ad a-d conversion rate selection (03c1 16 , 03c0 16 ) (03c3 16 , 03c2 16 ) (03c5 16 , 03c4 16 ) (03c7 16 , 03c6 16 ) (03c9 16 , 03c8 16 ) (03cb 16 , 03ca 16 ) (03cd 16 , 03cc 16 ) (03cf 16 , 03ce 16 ) cks1=1 cks0=0 a-d register 0(16) a-d register 1(16) a-d register 2(16) a-d register 3(16) a-d register 4(16) a-d register 5(16) a-d register 6(16) a-d register 7(16) resistor ladder successive conversion register a-d control register 0 (address 03d6 16 ) a-d control register 1 (address 03d7 16 ) v ref v in data bus high-order data bus low-order v ref vcut=0 av ss vcut=1 cks0=1 cks1=0 decoder comparator addresses p6 0 /an 0 p6 1 /an 1 p6 2 /an 2 p6 3 /an 3 p6 5 /an 5 p6 6 /an 6 p6 7 /an 7 p6 4 /an 4 ch2,ch1,ch0=000 ch2,ch1,ch0=001 ch2,ch1,ch0=010 ch2,ch1,ch0=011 ch2,ch1,ch0=100 ch2,ch1,ch0=101 ch2,ch1,ch0=110 ch2,ch1,ch0=111 p5 0 /an 50 p5 2 /an 52 p5 3 /an 53 p5 4 /an 54 p5 1 /an 51 ch2,ch1,ch0=000 ch2,ch1,ch0=001 ch2,ch1,ch0=010 ch2,ch1,ch0=011 ch2,ch1,ch0=100 adgsel0=0 adgsel0=1 port p6 group port p5 group
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer a-d converter 91 figure 1.83. a-d converter-related registers (1) a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 repeat sweep mode 1 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit adgsel0 a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : vref not connected 1 : vref connected a-d input group select bit w r b2 b1 b0 b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 0 : port p6 group is selected 1 : port p5 group is selected note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: an 50 to an 54 can be used in the same way as for an 0 to an 4 . frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: an 50 to an 54 can be used in the same way as for an 0 to an 4 . note 3: if the repeat sweep mode is selected for the port p5 group, the contents of a-d registers 5 to 7 are indeterminate. aa a aa a aa a aa aa a a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a a a aa aa 0 set this bit to 0. (note 2, 3) 0 set this bit to 0.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer a-d converter 92 figure 1.84. a-d converter-related registers (2) a-d control register 2 (note) symbol address when reset adcon2 03d4 16 xxxx0000 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 : without sample and hold 1 : with sample and hold bit symbol bit name function r w note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. a a a a nothing is assigned. when write, set "0". when read, their content is indeterminate. a-d register i symbol address when reset adi(i=0 to 7) 03c0 16 to 03cf 16 indeterminate eight low-order bits of a-d conversion result function r w (b15) b7 b7 b0 b0 (b8) during 10-bit mode two high-order bits of a-d conversion result nothing is assigned. when write, set "0". when read, their content is indeterminate. during 8-bit mode when read, the content is indeterminate a a a a smp 000 a a a a reserved bit always set to 0
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer a-d converter 93 (1) one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d conver- sion. (see table 1.31.) figure 1.85 shows the a-d control register in one-shot mode. figure 1.85. a-d conversion register in one-shot mode item specification function the pin selected by the analog input pin select bit is used for one a-d conversion start condition writing 1 to a-d conversion start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin one of an 0 to an 7 , as selected (note) reading of result of a-d converter read a-d register corresponding to selected pin note : an 50 to an 54 can be used in the same way as for an 0 to an 4 . a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit adgsel0 a-d operation mode select bit 1 1 : vref connected a-d input group select bit w r b2 b1 b0 b4 b3 0 : port p6 group is selected 1 : port p5 group is selected note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: an 50 to an 54 can be used in the same way as for an 0 to an 4 . frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. aa a aa a aa a aa a aa a aa aa a a aa a aa a aa aa a a aa a aa a aa a aa aa a a aa aa a a aa aa a a a a aa aa 0 set this bit to 0. 0 set this bit to 0. 00 0 1 invalid in one-shot mode set this bit to 0 in this mode. table 1.31. one-shot mode specifications
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer a-d converter 94 (2) repeat mode in repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conversion. (see table 1.32.) figure 1.86 shows the a-d control register in repeat mode. figure 1.86. a-d conversion register in repeat mode item specification function the pin selected by the analog input pin select bit is used for repeated a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin one of an 0 to an 7 , as selected (note) reading of result of a-d converter read a-d register corresponding to selected pin table 1.32. repeat mode specifications a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 1 : repeat mode md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit adgsel0 a-d operation mode select bit 1 1 : vref connected a-d input group select bit w r b2 b1 b0 b4 b3 0 : port p6 group is selected 1 : port p5 group is selected note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: an 50 to an 54 can be used in the same way as for an 0 to an 4 . frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a 0 set this bit to 0. 0 set this bit to 0. 01 0 1 invalid in repeat mode set this bit to 0 in this mode. note : an 50 to an 54 can be used in the same way as for an 0 to an 4 .
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer a-d converter 95 (3) single sweep mode in single sweep mode, the pins selected using the a-d sweep pin select bit are used for one-by-one a-d conversion. (see table 1.33.) figure 1.87 shows the a-d control register in single sweep mode. figure 1.87. a-d conversion register in single sweep mode item specification function the pins selected by the a-d sweep pin select bit are used for one-by-one a-d conversion start condition writing 1 to a-d converter start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0.) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins)(note) reading of result of a-d converter read a-d register corresponding to selected pin note : an 50 to an 54 can be used in the same way as for an 0 to an 4 . a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit invalid in single sweep mode ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 0 : single sweep mode md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit adgsel0 a-d operation mode select bit 1 1 : vref connected a-d input group select bit w r b4 b3 0 : port p6 group is selected 1 : port p5 group is selected note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: an 50 to an 54 can be used in the same way as for an 0 to an 4 . note 3: if port p5 group is selected, do not select 6 pins and 8 pins sweep mode. a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a 0 set this bit to 0. 0 set this bit to 0. 10 0 1 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 (note 2, 3) set this bit to 0 in this mode. table 1.33. single sweep mode specifications
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer a-d converter 96 (4) repeat sweep mode 0 in repeat sweep mode 0, the pins selected using the a-d sweep pin select bit are used for repeat sweep a-d conversion. (see table 1.34.) figure 1.88 shows the a-d control register in repeat sweep mode 0. figure 1.88. a-d conversion register in repeat sweep mode 0 item specification function the pins selected by the a-d sweep pin select bit are used for repeat sweep a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins)(note) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) table 1.34. repeat sweep mode 0 specifications note : an 50 to an 54 can be used in the same way as for an 0 to an 4 . a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit invalid in repeat sweep mode 0 ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit adgsel0 a-d operation mode select bit 1 1 : vref connected a-d input group select bit w r b4 b3 0 : port p6 group is selected 1 : port p5 group is selected note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: an 50 to an 54 can be used in the same way as for an 0 to an 4 . note 3: if port p5 group is selected, the contents of a-d registers 5 to 7 are indeterminate. a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa a a aa aa a a a a a a a a 0 set this bit to 0. 0 set this bit to 0. 11 0 1 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 (note 2, 3) set this bit to 0 in this mode.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer a-d converter 97 item specification function all pins perform repeat sweep a-d conversion, with emphasis on the pin or pins selected by the a-d sweep pin select bit example : an 0 selected an 0 an 1 an 0 an 2 an 0 an 3 , etc start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 (1 pin), an 0 and an 1 (2 pins), an 0 to an 2 (3 pins), an 0 to an 3 (4 pins) (note) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) (5) repeat sweep mode 1 in repeat sweep mode 1, all pins are used for a-d conversion with emphasis on the pin or pins selected using the a-d sweep pin select bit. (see table 1.35.) figure 1.89 shows the a-d control register in repeat sweep mode 1. figure 1.89. a-d conversion register in repeat sweep mode 1 table 1.35. repeat sweep mode 1 specifications a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit invalid in repeat sweep mode 1 ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 1 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit adgsel0 a-d operation mode select bit 1 set ??in this mode. 1 : vref connected a-d input group select bit w r b4 b3 0 : port p6 group is selected 1 : port p5 group is selected note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: an 50 to an 54 can be used in the same way as for an 0 to an 4 . note 3: if port p5 group is selected, the contents of a-d registers 5 to 7 are indeterminate. a aa a aa a a aa aa a a aa aa a aa a aa a aa a aa a a aa aa a aa a a aa aa a a aa aa a aa a aa a aa aa a 0 set this bit to 0. 0 set this bit to 0. 11 1 1 when single sweep and repeat sweep mode 1 are selected 0 0 : an 0 (1 pins) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 (note 2, 3) note : an 50 to an 54 can be used in the same way as for an 0 to an 4 .
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer a-d converter 98 ? sample and hold sample and hold is selected by setting bit 0 of the a-d control register 2 (address 03d4 16 ) to 1. when sample and hold is selected, the rate of conversion of each pin increases. as a result, a 28 f ad cycle is achieved with 8-bit resolution and 33 f ad with 10-bit resolution. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold is to be used.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer programmable i/o port 99 programmable i/o ports there are 43 programmable i/o ports: p0 to p7. each port can be set independently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. the port p1 allows the drive capacity of its n-channel output transistor to be set as necessary. figures 1.90 to 1.92 show the programmable i/o ports. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices, they function as outputs regardless of the contents of the direction registers. see the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) direction registers figure 1.93 shows the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these regis- ters corresponds one for one to each i/o pin. (2) port registers figure 1.94 shows the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in port registers corresponds one for one to each i/o pin. (3) pull-up control registers figure 1.95 shows the pull-up control registers. the pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. (4) port p1 drive capacity control register figure 1.95 shows a structure of the port p1 drive capacity control register. this register is used to control the drive capacity of the port p1's n-channel output transistor. each bit in this register corresponds one for one to the port pins.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer programmable i/o port 100 figure 1.90. programmable i/o ports (1) p3 0 to p3 5 data bus direction register pull-up selection port latch p0 0 to p0 7 , p4 2 , p7 1 data bus pull-up selection input to respective peripheral functions direction register port latch p4 1 , p7 0 data bus pull-up selection output direction register port latch p4 0 , p4 3 , p4 4 data bus pull-up selection output input to respective peripheral functions direction register port latch
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer programmable i/o port 101 figure 1.91. programmable i/o ports (2) p1 0 to p1 7 data bus pull-up selection drive capacity control register direction register port latch p5 0 , p5 3 , p5 4 data bus pull-up selection output direction register port latch analog input p5 2 data bus pull-up selection output direction register port latch analog input serial clock input p5 1 data bus pull-up selection analog input port latch direction register serial i/o input
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer programmable i/o port 102 figure 1.92. programmable i/o ports (3) p6 0 to p6 7 data bus pull-up selection analog input port latch direction register
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer programmable i/o port 103 figure 1.93. direction register port pi direction register (note 1) symbol address when reset pdi (i = 0 to 7) 03e2 16 , 03e3 16 , 03e7 16 , 03ea 16 , 00 16 03eb 16 , 03ee 16 , 03ef 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 direction register pdi_1 port pi 1 direction register pdi_2 port pi 2 direction register pdi_3 port pi 3 direction register pdi_4 port pi 4 direction register pdi_5 port pi 5 direction register pdi_6 port pi 6 direction register pdi_7 port pi 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) (i = 0 to 7 except 2) note 1: set bit 2 of protect register (address 000a 16 ) to ??before rewriting to the port p4 direction register. note 2: nothing is assigned in direction register of p3 6 , p3 7 , p4 6 , p4 7 , p5 5 to p5 7 , p7 2 to p7 7 . these bits can either be set nor reset. when read, its contents are indeterminate. a a a a a a a a a a a a a a a a a a a a
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer programmable i/o port 104 figure 1.94. port register port pi register bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pi_0 port pi 0 register pi_1 port pi 1 register pi_2 port pi 2 register pi_3 port pi 3 register pi_4 port pi 4 register pi_5 port pi 5 register pi_6 port pi 6 register pi_7 port pi 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data (i = 0 to 7 except 2) a a a a a a a a a a a a a a a a a a a a a a symbol address when reset pi (i = 0 to 7) 03e0 16 , 03e1 16 , 03e5 16 , 03e8 16 , indeterminate 03e9 16 , 03ec 16 , 03ed 16 indeterminate note: nothing is assigned in direction register of p3 6 , p3 7 , p4 6 , p4 7 , p5 5 to p5 7 , p7 2 to p7 7 . this bit can either be set nor reset. when read, its content is indeterminate.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer programmable i/o port 105 figure 1.95. pull-up control register pull-up control register 0 symbol address when reset pur0 03fc 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu00 p0 0 to p0 3 pull-up pu01 p0 4 to p0 7 pull-up pu02 p1 0 to p1 3 pull-up pu03 p1 4 to p1 7 pull-up pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 5 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high a aa a a aa aa a aa a aa a aa a aa a a aa aa a aa pull-up control register 1 symbol address when reset pur1 03fd 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu10 p4 0 to p4 3 pull-up pu11 p4 4 to p4 7 pull-up pu12 p5 0 to p5 3 pull-up pu13 p5 4 pull-up pu14 p6 0 to p6 3 pull-up pu15 p6 4 to p6 7 pull-up pu16 p7 0 to p7 1 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high a a aa aa a aa a a aa aa a aa a aa a aa a aa a a aa aa port p1 drive capacity control register symbol address when reset drr 03fe 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 drr0 port p1 0 drive capacuty drr1 port p1 1 drive capacuty drr2 port p1 2 drive capacuty drr3 port p1 3 drive capacuty drr4 port p1 4 drive capacuty drr5 port p1 5 drive capacuty drr6 port p1 6 drive capacuty drr7 port p1 7 drive capacuty set p1 n-channel output transistor drive capacity 0 : low 1 : high a aa a a aa aa a aa a aa a a aa aa a aa a a aa aa a aa
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer programmable i/o port 106 example connection of unused pins table 1.36. example connection of unused pins pin name connection ports p0, p1, p3 to p7 x out (note) av ss , v ref av cc after setting for input mode, connect every pin to v ss (pull-down); or after setting for output mode, leave these pins open. open connect to v cc connect to v ss note: with external clock input to x in pin.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer usage precaution 107 usage precaution timer a (timer mode) (1) reading the timer a0 register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer a0 register with the reload timing gets ffff 16 . reading the timer a0 register after setting a value in the timer a0 register with a count halted but before the counter starts counting gets a proper value. timer a (event counter mode) (1) reading the timer a0 register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer a0 register with the reload timing gets ffff 16 by under- flow or 0000 16 by overflow. reading the timer a0 register after setting a value in the timer a0 register with a count halted but before the counter starts counting gets a proper value. (2) when stop counting in free run type, set timer again. timer a (one-shot timer mode) (1) setting the count start flag to 0 while a count is in progress causes as follows: ? the counter stops counting and a content of reload register is reloaded. ? the ta0 out pin outputs l level. ? the interrupt request generated and the timer a0 interrupt request bit goes to 1. (2) the timer a0 interrupt request bit goes to 1 if the timer's operation mode is set using any of the following procedures: ? selecting one-shot timer mode after reset. ? changing operation mode from timer mode to one-shot timer mode. ? changing operation mode from event counter mode to one-shot timer mode. therefore, to use timer a0 interrupt (interrupt request bit), set timer a0 interrupt request bit to 0 after the above listed changes have been made. timer a (pulse width modulation mode) (1) the timer a0 interrupt request bit becomes 1 if setting operation mode of the timer in compliance with any of the following procedures: ? selecting pwm mode after reset. ? changing operation mode from timer mode to pwm mode. ? changing operation mode from event counter mode to pwm mode. therefore, to use timer a0 interrupt (interrupt request bit), set timer a0 interrupt request bit to 0 after the above listed changes have been made. (2) setting the count start flag to 0 while pwm pulses are being output causes the counter to stop counting. if the ta0 out pin is outputting an h level in this instance, the output level goes to l, and the timer a0 interrupt request bit goes to 1. if the ta0 out pin is outputting an l level in this instance, the level does not change, and the timer a0 interrupt request bit does not becomes 1.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer usage precaution 108 timer b (timer mode, event counter mode) (1) reading the timer bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. reading the timer bi register with the reload timing gets ffff 16 . reading the timer bi register after setting a value in the timer bi register with a count halted but before the counter starts counting gets a proper value. timer b (pulse period/pulse width measurement mode) (1) if changing the measurement mode select bit is set after a count is started, the timer bi interrupt request bit goes to 1. (2) when the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. at this time, timer bi interrupt request is not generated. timer x (timer mode) (1) reading the timer xi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer xi register with the reload timing gets ffff 16 . reading the timer a0 register after setting a value in the timer xi register with a count halted but before the counter starts counting gets a proper value. timer x (event counter mode) (1) reading the timer xi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer xi register with the reload timing gets ffff 16 by underflow or 0000 16 by overflow. reading the timer xi register after setting a value in the timer xi register with a count halted but before the counter starts counting gets a proper value. (2) when stop counting in free run type, set timer again. timer x (one-shot timer mode) (1) setting the count start flag to 0 while a count is in progress causes as follows: ? the counter stops counting and a content of reload register is reloaded. ? the txi inout pin outputs l level. ? the interrupt request generated and the timer xi interrupt request bit goes to 1. (2) the timer xi interrupt request bit goes to 1 if the timer's operation mode is set using any of the following procedures: ? selecting one-shot timer mode after reset. ? changing operation mode from timer mode to one-shot timer mode. ? changing operation mode from event counter mode to one-shot timer mode. therefore, to use timer xi interrupt (interrupt request bit), set timer xi interrupt request bit to 0 after the above listed changes have been made.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer usage precaution 109 timer x (pulse width modulation mode) (1) the timer xi interrupt request bit becomes 1 if setting operation mode of the timer in compliance with any of the following procedures: ? selecting pwm mode after reset. ? changing operation mode from timer mode to pwm mode. ? changing operation mode from event counter mode to pwm mode. therefore, to use timer xi interrupt (interrupt request bit), set timer xi interrupt request bit to 0 after the above listed changes have been made. (2) setting the count start flag to 0 while pwm pulses are being output causes the counter to stop counting. if the txi inout pin is outputting an h level in this instance, the output level goes to l, and the timer xi interrupt request bit goes to 1. if the txi inout pin is outputting an l level in this instance, the level does not change, and the timer xi interrupt request bit does not becomes 1. timer x (pulse period/pulse width measurement mode) (1) if changing the measurement mode select bit is set after a count is started, the timer xi interrupt request bit goes to 1. (2) when the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. at this time, timer xi interrupt request is not generated. a-d converter (1) write to each bit (except bit 6) of a-d control register 0, to each bit of a-d control register 1, and to bit 0 of a-d control register 2 when a-d conversion is stopped (before a trigger occurs). in particular, when the vref connection bit is changed from 0 to 1, start a-d conversion after an elapse of 1 m s or longer. (2) when changing a-d operation mode, select analog input pin again. (3) using one-shot mode or single sweep mode read the correspondence a-d register after confirming a-d conversion is finished. (it is known by a- d conversion interrupt request bit.) (4) using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 use the undivided main clock as the internal cpu clock. stop mode and wait mode ____________ (1) when returning from stop mode by hardware reset, reset pin must be set to l level until main clock oscillation is stabilized. (2) when shifting to wait mode or stop mode, the program stops after reading 8 bytes from the wait instruction and the instruction that sets all clock stop bits to 1 in the instruction queue. therefore, insert a minimum of 8 nops after the wait instruction and the instruction that sets all clock stop bits to 1.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer usage precaution 110 interrupts (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an inter- rupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. concerning the first instruction immediately after reset, generating any interrupt is prohibited. (3) external interrupt ________ ________ ? when changing a polarity of pins int0 and int1, the interrupt request bit may become "1". clear the interrupt request bit after changing the polarity. (4) changing interrupt control register see "changing interrupt control register".
electrical characteristics (vcc = 5v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 111 table 1.37. absolute maximum ratings note 1: when writing to frash mcu, cnvss is C0.3 to 13 (v) . note 3: extended operating temperature version: -40 to 85 c. note 2: flat package (56p6s-a) is 300 mw. note 4: extended operating temperature version: -65 to 150 c. p7 0 , p7 1 , v ref , x in reset, cnvss, v o - 0.3 to vcc + 0.3 (note 1) - 0.3 to vcc + 0.3 p d ta = 25 ? - 0.3 to 7 - 0.3 to 7 v v v ? v i avcc vcc t stg t opr ? mw v - 40 to 150 (note 4) 1000 (note 2) - 20 to 85 (note 3) p4 0 to p4 5 , p5 0 to p5 4, p6 0 to p6 7 , p0 0 to p0 7 , p1 0 to p1 7, p3 0 to p3 5 , p7 0 , p7 1 , v ref , x in p5 0 to p5 4, p6 0 to p6 7 , p0 0 to p0 7 , p1 0 to p1 7, p3 0 to p3 5 , p4 0 to p4 5 , parameter unit rated value condition symbol operating ambient temperature input voltage analog supply voltage supply voltage output voltage power dissipation storage temperature electrical characteristics
electrical characteristics (vcc = 5v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 112 v cc = 5v 2.7 5.5 vcc 5.0 vcc avcc v v 0 0 vss avss 0.8vcc v v v vcc 0.2vcc 0 - 5.0 - 10.0 10.0 5.0 f (x in ) mhz i ol (peak) ma 10 f (xc in ) khz 50 32.768 v v cc =4.0v to 5.5v with wait 5 x v cc mhz p5 0 to p5 4, p6 0 to p6 7 , p7 0 , p7 1 , x in , reset, cnv ss , v ih v il i oh (avg) i oh (peak) i ol (peak) p1 0 to p1 7 i ol (avg) ma ma ma ma 30.0 p0 0 to p0 7 , p1 0 to p1 7, p3 0 to p3 5 , p4 0 to p4 5 , p5 0 to p5 4, p6 0 to p6 7, p7 0, p7 1, x in, reset, cnv ss p0 0 to p0 7 , p1 0 to p1 7, p3 0 to p3 5 , p4 0 to p4 5 , p5 0 to p5 4, p6 0 to p6 7 , p7 0 , p7 1 p0 0 to p0 7 , p1 0 to p1 7, p3 0 to p3 5 , p4 0 to p4 5 , p5 0 to p5 4, p6 0 to p6 7 , p7 0 , p7 1 p0 0 to p0 7 , p3 0 to p3 5 , p4 0 to p4 5 , p5 0 to p5 4, p6 0 to p6 7 , p7 0 , p7 1 p0 0 to p0 7 , p1 0 to p1 7, p3 0 to p3 5 , p4 0 to p4 5 , p5 0 to p5 4, p6 0 to p6 7 , p7 0 , p7 1 p0 0 to p0 7 , p3 0 to p3 5 , p4 0 to p4 5 , i ol (avg) p1 0 to p1 7 15.0 ma 10.0 highpower lowpower highpower lowpower 5.0 0 0 v cc =2.7v to 4.0v - 10.000 mhz 10 v cc =4.0v to 5.5v 2.31 x v cc mhz 0 0 v cc =2.7v to 4.0v +0.760 without wait typ. max. unit parameter symbol min standard supply voltage (note 2) analog supply voltage analog supply voltage supply voltage low input voltage high input voltage high average output current high peak output current low peak output current main clock input oscillation frequency low average output current subclock oscillation frequency low peak output current low average output current mask rom version flash memory version 4.0 5.5 5.0 mask rom version flash memory version mhz 10 v cc =4.0v to 5.5v 0 mask rom version flash memory version mhz 10 v cc =4.0v to 5.5v 0 note 1: unless otherwise noted: v cc = 2.7v to 5.5v, vss = 0v, ta = C 20 to 85 o c (extended operating temperature version:C 40 to 85 o c). flash version: v cc = 4.0v to 5.5v, vss = 0v, ta = C 20 to 85 o c (extended operating temperature version:C 40 to 85 o c.) note 2: flash version: v cc = 4.0v to 5.5v note 3: the average output current is an average value measured over 100ms. note 4: keep output current as follows: the sum of port p3 and p4 i ol (peak) is under 40 ma. the sum of port p1 i ol (peak) is under 60 ma. the sum of port p1, p3 and p4 i oh (peak) is under 40 ma. the sum of port p0, p5, p6 and p7 i ol (peak) is under 80 ma. the sum of port p0, p5, p6 and p7 i oh (peak) is under 80 ma. table 1.38. recommended operating conditions (note 1) aaa aaa aaa 5.5 4.0 2.7 0.0 3.5 10.0 main clock input oscillation frequency (without wait) power supply voltage [v] ( m a in c l oc k : n o d ivi s i o n ) highest operation frequency [mhz] 5 x vcc - 10.000mhz aaa aaa aaa 5.5 4.0 2.7 0.0 10.0 main clock input oscillation frequency (with wait) power supply voltage [v] ( m a in c l oc k : n o d ivi s i o n ) highest operation frequency [mhz ] 7.0 2.31 x v cc + 0.760mhz
electrical characteristics (vcc = 5v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 113 table 1.39. electrical characteristics (note1) v oh v oh v ol v 4.7 v 2.0 3.0 i oh = - 5 ma i oh = - 200 a i ol = 5 ma p0 0 to p0 7 ,p1 0 to p1 7 ,p3 0 to p3 5 , p4 0 to p4 5 ,p5 0 to p5 4 ,p6 0 to p6 7 , p0 0 to p0 7 ,p1 0 to p1 7 ,p3 0 to p3 5 , p4 0 to p4 5 ,p5 0 to p5 4 ,p6 0 to p6 7 , v p0 0 to p0 7 ,p3 0 to p3 5 ,p4 0 to p4 5 p5 0 to p5 4 ,p6 0 to p6 7 ,p7 0 ,p7 1 v ol i ol = 200 a 0.45 v v ol p1 0 to p1 7 i ol = 15ma v 2.0 i ol = 200 a 0.3 v v ol p1 0 to p1 7 p7 0 ,p7 1 p7 0 ,p7 1 p0 0 to p0 7 ,p3 0 to p3 5 ,p4 0 to p4 5 p5 0 to p5 4 ,p6 0 to p6 7 ,p7 0 ,p7 1 i ih v ram icc v t+ -v t- v t+ -v t- 0.2 0.8 v 0.2 1.8 v 5.0 ? ? when clock is stopped 2.0 v 1.0 ? ma 20.0 reset ta0 in ,tx0 inout ,tx1 inout ,tx2 inout tb0 in ,tb1 in int 0 ,int 1 ,clk 0 ,ki 0 to ki 7 v i = 5v v i = 0v -5.0 19.0 38.0 4.0 ? 90.0 p0 0 to p0 7 ,p1 0 to p1 7 ,p3 0 to p3 5 , p4 0 to p4 5 ,p5 0 to p5 4 ,p6 0 to p6 7 p7 0 ,p7 1 , reset, cnvss i il p0 0 to p0 7 ,p1 0 to p1 7 ,p3 0 to p3 5 , p4 0 to p4 5 ,p5 0 to p5 4 ,p6 0 to p6 7 , v oh x out highpower lowpower v 3.0 3.0 v ol x out highpower lowpower v 2.0 2.0 i oh = 1 ma i oh = 0.5 ma i oh = - 1 ma i oh = - 0.5 ma highpower i ol = 5 ma 2.0 lowpower i ol = 200 a 0.45 highpower lowpower k w 167.0 50.0 30.0 symbol standard typ. unit measuring condition min. max. parameter high output voltage low output voltage low output voltage low output voltage hysteresis hysteresis high input current low input current ram retention voltage power supply current high output voltage high output voltage low output voltage low output voltage f(x in )=10mhz square wave, no division f(x cin )=32khz square wave ta=25 c when clock is stopped ta=85 c when clock is stopped i/o pin has no load f(x cin )=32khz with wait(note2) v oh x cout highpower lowpower v 3.0 1.6 no load no load high output voltage v ol x out highpower lowpower v 0 0 low output voltage v i = 0v r pullup p0 0 to p0 7 ,p1 0 to p1 7 ,p3 0 to p3 5 , p4 0 to p4 5 ,p5 0 to p5 4 ,p6 0 to p6 7 , p7 0 ,p7 1 pull-up resistor p7 0 ,p7 1 , reset, cnvss m w 1.0 r xin x in feedback resistor m w 6.0 r xcin x cin feedback resistor ? no load no load rxd 0 , rxd 1 note 1: unless otherwise noted: v cc = 5v, v ss = 0v at ta = 25 o c, f(x in ) = 10mhz) note 2: with one timer operated using f c32 . v cc = 5v
electrical characteristics (vcc = 5v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 114 table 1.40. a-d conversion characteristics v cc = 5v bits lsb v ref =v cc ? 10 v ref =v cc = 5v r ladder t conv kohm ? v v ia v ref v 0 2 10 v cc v ref 40 3.3 ? 2.8 t conv t samp 0.3 ? v ref =v cc v ref =v cc = 5v lsb ? v ref = v cc = 5v ? lsb symbol standard typ. unit measuring condition min. max. parameter resolution absolute accuracy ladder resistance conversion time(10bit) reference voltage analog input voltage conversion time(8bit) sampling time sample & hold function not available sample & hold function available(10bit) sample & hold function available(8bit)
electrical characteristics (vcc = 5v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 115 table 1.42. timer a input (counter input in event counter mode) table 1.43. timer a input (gating input in timer mode) table 1.44. timer a input (external trigger input in one-shot timer mode) table 1.45. timer a input (external trigger input in pulse width modulation mode) table 1.46. timer a input (up/down input in event counter mode) timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table 1.41. external clock input ns t r ns ns ns ns t c t w(h ) t w(l) t f parameter symbol standard unit min. max. external clock input low pulse width external clock input high pulse width external clock input cycle time external clock fall time external clock rise time 15 100 40 40 15 ns t w(tal) ns ns t w(tah) t c(ta) ns ns ns t c(ta) t w(tah) t w(tal) ns ns ns t c(ta) t w(tah) t w(tal) ns ns t w(tah) t w(tal) ns ns ns ns ns t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 40 100 40 400 200 200 200 100 100 100 100 2000 1000 1000 400 400 ta0 in input low pulse width ta0 in input high pulse width parameter symbol ta0 in input cycle time standard unit min. max. symbol symbol symbol symbol parameter parameter parameter parameter standard unit min. max. standard unit min. max. standard unit min. max. standard unit min. max. ta0 in input low pulse width ta0 in input high pulse width ta0 in input cycle time ta0 in input low pulse width ta0 in input high pulse width ta0 in input cycle time ta0 in input low pulse width ta0 in input high pulse width ta0 out input low pulse width ta0 out input high pulse width ta0 out input cycle time ta0 out input hold time ta0 out input setup time v cc = 5v
electrical characteristics (vcc = 5v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 116 ns ns ns t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbl) t w(tbh) ns ns ns ns ns t c(tb) t w(tbh) t w(tbl) ns ns ns t c(tb) t w(tbl) ns t w(tbh) ns ns t c(tx) t w(txh) t w(txl) ns ns ns t c(tx) t w(txl) ns t w(txh) ns ns t c(tx) t w(txl) ns t w(txh) parameter symbol standard unit min. max. parameter symbol standard unit min. max. parameter symbol standard unit min. max. parameter symbol standard unit min. max. parameter symbol standard unit min. max. parameter symbol standard unit min. max. txi inout input low pulse width txi inout input high pulse width txi inout input cycle time txi inout input low pulse width txi inout input high pulse width txi inout input cycle time txi inout input low pulse width txi inout input high pulse width txi inout input cycle time tbi in input low pulse width tbi in input high pulse width tbi in input cycle time tbi in input low pulse width tbi in input high pulse width tbi in input cycle time tbi in input low pulse width (counted on both edges) tbi in input high pulse width (counted on both edges) tbi in input cycle time (counted on both edges) tbi in input low pulse width (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input cycle time (counted on one edge) 100 40 40 80 80 200 400 200 200 400 200 200 100 40 40 400 200 200 200 100 100 timing requirements (referenced to v cc = 5v, vss = 0v at ta = 25 o c unless otherwise specified) table 1.47. timer b input (counter input in event counter mode) table 1.48. timer b input (pulse period measurement mode) table 1.49. timer b input (pulse width measurement mode) table 1.50. timer x input (counter input in event counter mode) table 1.51. timer x input (gate input in timer mode) table 1.52. timer x input (external trigger input in one-shot timer mode) v cc = 5v
electrical characteristics (vcc = 5v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 117 table 1.53. timer x input (pulse period measurement mode) table 1.54. timer x input (pulse width measurement mode) table 1.55. serial i/o ns ns t c(tx) t w(txh) t w(txl) ns ns ns t c(tx) t w(txl) ns t w(txh) ns ns t w(inh) t w(inl) ns ns ns ns ns ns ns t c(ck) t w(ckh) t w(ckl) t d(c-q) t su(d-c) t h(c-q) t h(c-d) parameter symbol standard unit min. max. parameter symbol standard unit min. max. parameter symbol standard unit min. max. parameter symbol standard unit min. max. txi inout input low pulse width txi inout input high pulse width txi inout input cycle time txi inout input low pulse width txi inout input high pulse width txi inout input cycle time clk0 input cycle time clk0 input high pulse width clk0 input low pulse width txdi hold time rxdi input setup time txdi output delay time rxdi input hold time inti input low pulse width inti input high pulse width 400 200 200 400 200 200 250 250 200 100 100 0 30 90 80 _______ table 1.56. external interrupt inti inputs v cc = 5v timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified)
electrical characteristics (vcc = 5v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 118 t su(d?) ta0 in input ta0 out input during event counter mode tbi in input clk0 txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c?) t h(c?) t h(c?) t h(t in ?p) t su(up? in ) ta0 in input (when count on falling edge is selected) ta0 in input (when count on rising edge is selected) ta0 out input (up/down input) inti input txi inout input t c(tx) t w(txh) t w(txl) v cc = 5v
electrical characteristics (vcc = 3v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 119 table 1.57. electrical characteristics (note 1) v oh v ol v v 0.5 2.5 i oh = - 1ma i ol = 1 ma p0 0 to p0 7 ,p1 0 to p1 7 ,p3 0 to p3 5 , p4 0 to p4 5 ,p5 0 to p5 4 ,p6 0 to p6 7 , p0 0 to p0 7 ,p3 0 to p3 5 ,p4 0 to p4 5 p5 0 to p5 4 ,p6 0 to p6 7 ,p7 0 ,p7 1 v ol p1 0 to p1 7 i ol = 3 ma v 0.5 p7 0 ,p7 1 i ih v ram icc v t+ -v t- v t+ -v t- 0.2 0.8 v 0.2 1.8 v 4.0 ? ? when clock is stopped 2.0 v 1.0 ? ma 20.0 reset v i = 3v v i = 0v -4.0 6.0 15.0 2.8 ? 40.0 p0 0 to p0 7 ,p1 0 to p1 7 ,p3 0 to p3 5 , p4 0 to p4 5 ,p5 0 to p5 4 ,p6 0 to p6 7 , p7 0 ,p7 1 , reset, cnvss i il p0 0 to p0 7 ,p1 0 to p1 7 ,p3 0 to p3 5 , p4 0 to p4 5 ,p5 0 to p5 4 ,p6 0 to p6 7 , v oh x out highpower lowpower v 2.5 2.5 v ol x out highpower lowpower v 0.5 0.5 i oh = 0.1 ma i oh = 50 a i oh = - 1 ma i oh = - 50 a highpower i ol = 1 ma 0.5 lowpower k w 500.0 120.0 66.0 symbol standard typ. unit measuring condition min. max. parameter high output voltage low output voltage low output voltage hysteresis hysteresis high input current low input current ram retention voltage power supply current high output voltage low output voltage f(x in )=7mhz square wave, no division f(x cin )=32khz with wait. oscillation capacity high (note 2) ta=25 c when clock is stopped ta=85 c when clock is stopped i/o pin has no load f(x cin )=32khz with wait. oscillation capacity low (note 2) v oh x cout highpower lowpower v 3.0 1.6 no load no load high output voltage v ol x out highpower lowpower v 0 0 low output voltage v i = 0v r pullup p0 0 to p0 7 ,p1 0 to p1 7 ,p3 0 to p3 5 , p4 0 to p4 5 ,p5 0 to p5 4 ,p6 0 to p6 7 , p7 0 ,p7 1 pull-up resistor p7 0 ,p7 1 , reset, cnvss m w 3.0 r xin x in feedback resistor m w 10.0 r xin x in feedback resistor ? no load no load f(x cin )=32khz square wave 0.9 ? ta0 in ,tx0 inout ,tx1 inout ,tx2 inout tb0 in ,tb1 in int 0 ,int 1 ,clk 0 ,ki 0 to ki 7 rxd 0 , rxd 1 note 1: unless otherwise noted: v cc = 3v, v ss = 0v at ta = 25 o c, f(x in ) = 7mhz, with wait) note 2: with one timer operated using f c32 . v cc = 3v
electrical characteristics (vcc = 3v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 120 table 1.58. a-d conversion characteristics v cc = 3v bits lsb v ref =v cc ? 10 v ref =v cc = 3v, ad = f ad /2 r ladder kohm v v ia v ref v 0 2.7 10 v cc v ref 40 ? 14.0 t conv v ref =v cc symbol standard typ. unit measuring condition min. max. parameter resolution absolute accuracy ladder resistance reference voltage analog input voltage conversion time(8bit) sample & hold function not available (8bit) v cc = 3v
electrical characteristics (vcc = 3v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 121 table 1.60. timer a input (counter input in event counter mode) table 1.61. timer a input (gating input in timer mode) table 1.62. timer a input (external trigger input in one-shot timer mode) table 1.63. timer a input (external trigger input in pulse width modulation mode) table 1.64. timer a input (up/down input in event counter mode) timing requirements (referenced to v cc = 3v, v ss = 0v at ta = 25 o c unless otherwise specified) table 1.59. external clock input ns t r ns ns ns ns t c t w(h ) t w(l) t f parameter symbol standard unit min. max. external clock input low pulse width external clock input high pulse width external clock input cycle time external clock fall time external clock rise time 18 143 60 60 18 v cc = 3v ns t w(tal) ns ns t w(tah) t c(ta) ns ns ns t c(ta) t w(tah) t w(tal) ns ns ns t c(ta) t w(tah) t w(tal) ns ns t w(tah) t w(tal) ns ns ns ns ns t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 60 150 60 600 300 300 300 150 150 150 150 3000 1500 1500 600 600 ta0 in input low pulse width ta0 in input high pulse width parameter symbol ta0 in input cycle time standard unit min. max. symbol symbol symbol symbol parameter parameter parameter parameter standard unit min. max. standard unit min. max. standard unit min. max. standard unit min. max. ta0 in input low pulse width ta0 in input high pulse width ta0 in input cycle time ta0 in input low pulse width ta0 in input high pulse width ta0 in input cycle time ta0 in input low pulse width ta0 in input high pulse width ta0 out input low pulse width ta0 out input high pulse width ta0 out input cycle time ta0 out in p ut hold time ta0 out input setup time
electrical characteristics (vcc = 3v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 122 ns ns ns t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbl) t w(tbh) ns ns ns ns ns t c(tb) t w(tbh) t w(tbl) ns ns ns t c(tb) t w(tbl) ns t w(tbh) ns ns t c(tx) t w(txh) t w(txl) ns ns ns t c(tx) t w(txl) ns t w(txh) ns ns t c(tx) t w(txl) ns t w(txh) parameter symbol standard unit min. max. parameter symbol standard unit min. max. parameter symbol standard unit min. max. parameter symbol standard unit min. max. parameter symbol standard unit min. max. parameter symbol standard unit min. max. txi inout input low pulse width txi inout input high pulse width txi inout input cycle time txi inout input low pulse width txi inout input high pulse width txi inout input cycle time txi inout input low pulse width txi inout input high pulse width txi inout input cycle time tbi in input low pulse width tbi in input high pulse width tbi in input cycle time tbi in input low pulse width tbi in input high pulse width tbi in input cycle time tbi in input low pulse width (counted on both edges) tbi in input high pulse width (counted on both edges) tbi in input cycle time (counted on both edges) tbi in input low pulse width (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input cycle time (counted on one edge) 150 60 60 160 160 300 600 300 300 600 300 300 150 60 60 600 300 300 300 150 150 timing requirements (referenced to v cc = 3v, v ss = 0v at ta = 25 o c unless otherwise specified) table 1.65. timer b input (counter input in event counter mode) table 1.66. timer b input (pulse period measurement mode) table 1.67. timer b input (pulse width measurement mode) table 1.68. timer x input (counter input in event counter mode) table 1.69. timer x input (gate input in timer mode) table 1.70. timer x input (external trigger input in one-shot timer mode) v cc = 3v
electrical characteristics (vcc = 3v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 123 timing requirements (referenced to v cc = 3v, v ss = 0v at ta = 25 o c unless otherwise specified) table 1.71. timer x input (pulse period measurement mode) table 1.72. timer x input (pulse width measurement mode) table 1.73. serial i/o ns ns t c(tx) t w(txh) t w(txl) ns ns ns t c(tx) t w(txl) ns t w(txh) ns ns t w(inh) t w(inl) ns ns ns ns ns ns ns t c(ck) t w(ckh) t w(ckl) t d(c-q) t su(d-c) t h(c-q) t h(c-d) parameter symbol standard unit min. max. parameter symbol standard unit min. max. parameter symbol standard unit min. max. parameter symbol standard unit min. max. txi inout input low pulse width txi inout input high pulse width txi inout input cycle time txi inout input low pulse width txi inout input high pulse width txi inout input cycle time clk0 input cycle time clk0 input high pulse width clk0 input low pulse width txdi hold time rxdi input setup time txdi output delay time rxdi input hold time inti input low pulse width inti input high pulse width 600 300 300 600 300 300 380 380 300 150 150 0 50 90 160 v cc = 3v _______ table 1.74. external interrupt inti inputs
electrical characteristics (vcc = 3v) under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 124 t su(d?) ta0 in input ta0 out input during event counter mode tbi in input clk0 txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c?) t h(c?) t h(c?) t h(t in ?p) t su(up? in ) ta0 in input (when count on falling edge is selected) ta0 in input (when count on rising edge is selected) ta0 out input (up/down input) inti input txi inout input t c(tx) t w(txh) t w(txl) v cc = 3v
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer description preliminary 125 item power supply voltage program/erase voltage flash memory operation mode erase block division program method erase method program/erase control method number of commands program/erase count rom code protect performance 4.0v to 5.5 v (f(x in )=10mhz) v pp =12v 5% (f(x in )=10mhz) three modes (parallel i/o, standard serial i/o, cpu rewrite) see figure 1.aa.3. one division (4 kbytes) (note 1) in units of byte collective erase program/erase control by software command 6 commands 100 times parallel i/o mode is supported. note: the boot rom area contains a standard serial i/o mode control program which is stored in it when shipped from the factory. this area can be erased and programmed in only parallel i/o mode. user rom area boot rom area v cc =5v 5% (f(x in )=10mhz) table aa-1. outline performance of the m30201 (flash memory version) outline performance table aa-1 shows the outline performance of the m30201 (flash memory version).
description under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer preliminary 126 flash memory the m30201 (flash memory version) contains the nor type of flash memory that requires a high-voltage v pp power supply for program/erase operations, in addition to the v cc power supply for device operation. for this flash memory, three flash memory modes are available in which to read, program, and erase: parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a program- mer and a cpu rewrite mode in which the flash memory can be manipulated by the central processing unit (cpu). each mode is detailed in the pages to follow. in addition to the ordinary user rom area to store a microcomputer operation control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the users application system. this boot rom area can be rewritten in only parallel i/o mode. figure aa-3. block diagram of flash memory version sfr ram sfr ram sfr ram 00000 16 00400 16 yyyyy 16 df000 16 dfdff 16 xxxxx 16 fffff 16 m30201f6 xxxxx 16 f4000 16 yyyyy 16 00bff 16 microcomputer mode parallel i/o mode cpu rewrite mode standard serial i/o mode boot rom area (3.5k bytes) boot rom area (3.5k bytes) user rom area user rom area user rom area collective erasable/ programmable area type no. note 1: in cpu rewrite and standard serial i/o modes, the user rom is the only erasable/programmable area. note 2: in parallel i/o mode, the area to be erased/programmed can be selected by the address a17 input. the user rom area is selected when this address input is high and the boot rom area is selected when this address input is low. collective erasable/ programmable area collective erasable/ programmable area
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer cpu rewrite mode preliminary 127 cpu rewrite mode in cpu rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the central processing unit (cpu). in cpu rewrite mode, the flash memory can be operated on by reading or writing to the flash memory control register and flash command register. figure bb-1, figure bb- 2 show the flash memory control register, and flash command register respectively. also, in cpu rewrite mode, the cnv ss pin is used as the v pp power supply pin. apply the power supply voltage, v pp h, from an external source to this pin. in cpu rewrite mode, only the user rom area shown in figure aa-3 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block commands are issued for only the user rom area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite control program must be transferred to internal ram before it can be executed. flash memory control register 0 symbol address when reset fcon0 03b4 16 00100000 2 w r b7 b6 b5 b4 b3 b2 b1 b0 cpu rewrite mode select bit fcon00 bit symbol bit name function rw 0: cpu rewrite mode is invalid 1: cpu rewrite mode is valid this bit can not write. the value, if read, turns out to be indeterminate. reserved bit cpu rewrite mode monitor flag 0: cpu rewrite mode is invalid 1: cpu rewrite mode is valid must always be set to "0". nothing is assigned. in an attempt to write this bit, write "0". the value, if read, turns out to be "0". fcon02 0 a a a a a a reserved bit 0 1 must always be set to "1". reserved bit 0 a a must always be set to "0". reserved bit flash memory control register 1 symbol address when reset fcon1 03b5 16 xxxxxx00 2 w r b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function rw 0 a 0 reserved bit a nothing is assigned. in an attempt to write these bits, write "0". the value, if read, turns out to be indeterminate. must always be set to "0". a flash command register symbol address when reset fcmd 03b6 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 writing of software command read command "00 16 " program command "40 16 " program verify command "c0 16 " erase command "20 16 " + "20 16 " ?rase verify command "a0 16 " ?eset command "ff 16 " + "ff 6 " function rw a figure bb-1. flash memory control register figure bb-2. flash command register
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer cpu rewrite mode preliminary 128 microcomputer mode and boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the standard serial i/o mode becomes unusable.) see figure aa-3 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low (v ss ). in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset by pulling the p5 2 pin high (v cc ), the cnv ss pin high(v pph ), the cpu starts operating using the control program in the boot rom area. this mode is called the boot mode. the control program in the boot rom area can also be used to rewrite the user rom area. cpu rewrite mode operation procedure the internal flash memory can be operated on to program, read, verify, or erase it while being placed on- board by writing commands from the cpu to the flash memory control register (addresses 03b4 16 , 03b5 16 ) and flash command register (address 03b6 16 ). note that when in cpu rewrite mode, the boot rom area cannot be accessed for program, read, verify, or erase operations. before this can be accom- plished, a cpu write control program must be written into the boot rom area in parallel input/output mode. the following shows a cpu rewrite mode operation procedure. (1) apply v pp h to the cnv ss /v pp pin and v cc to the port p5 2 pin for reset release. or the user can jump from the user rom area to the boot rom area using the jmp instruction and execute the cpu write control program. in this case, set the cpu write mode select bit of the flash memory control register to 1 before applying v pp h to the cnv ss /v pp pin. (2) after transferring the cpu write control program from the boot rom area to the internal ram, jump to this control program in ram. (the operations described below are controlled by this program.) (3) set the cpu rewrite mode select bit to 1. (4) read the cpu rewrite mode monitor flag to see that the cpu rewrite mode is enabled. (5) execute operation on the flash memory by writing software commands to the flash command regis- ter. note 1: in addition to the above, various other operations need to be performed, such as for entering the data to be written to flash memory from an external source (e.g., serial i/o), initializing the ports, and writing to the watchdog timer. (1) apply v ss to the cnv ss /v pp pin. (2) set the cpu rewrite mode select bit to 0.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer cpu rewrite mode preliminary 129 precautions on cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. (1) operation speed during erase/program mode, set bclk to one of the following frequencies by changing the divide ratio: 5 mhz or less when wait bit (bit 7 at address 0005 16 ) = 0 (without internal access wait state) 10 mhz or less when wait bit (bit 7 at address 0005 16 ) = 1 (with internal access wait state) (2) instructions inhibited against use the instructions listed below cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory: und instruction, into instruction, jmps instruction, jsrs instruction, and brk instruction (3) interrupts inhibited against use no interrupts can be used that look up the fixed vector table in the flash memory area. maskable interrupts may be used by setting the interrupt vector table in a location outside the flash memory area.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer cpu rewrite mode preliminary 130 command program verify read program 03b6 16 first bus cycle second bus cycle 00 16 40 16 c0 16 write write write program address write read erase verify a0 16 write verify address verify data read erase 20 16 write 03b6 16 20 16 write verify address reset ff 16 write mode address mode address data (d 0 to d 7 ) data (d 0 to d 7 ) 03b6 16 03b6 16 03b6 16 03b6 16 03b6 16 program data verify data ff 16 write 03b6 16 software commands table bb-1 lists the software commands available with the m30201 (flash memory version). when cpu rewrite mode is enabled, write software commands to the flash command register to specify the operation to erase or program. the content of each software command is explained below. table bb-1. list of software commands (cpu rewrite mode) read command (00 16 ) the read mode is entered by writing the command code 00 16 to the flash command register in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (d 0 Cd 7 ), 8 bits at a time. the read mode is retained intact until another command is written. after reset and after the reset command is executed, the read mode is set. program command (40 16 ) the program mode is entered by writing the command code 40 16 to the flash command register in the first bus cycle. when the user execute an instruction to write byte data to the desired address (e.g., ste instruction) in the second bus cycle, the flash memory control circuit executes the program op- eration. the program operation requires approximately 20 m s. wait for 20 m s or more before the user go to the next processing. during program operation, the watchdog timer remains idle, with the value 7fff 16 set in it. note 1: the write operation is not completed immediately by writing a program command once. the user must always execute a program-verify command after each program command executed. and if verification fails, the user need to execute the program command repeatedly until the verification passes. see figure 1.bb.3 for an example of a programming flowchart.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer cpu rewrite mode preliminary 131 program-verify command (c0 16 ) the program-verify mode is entered by writing the command code c0 16 to the flash command register in the first bus cycle. when the user execute an instruction (e.g., lde instruction) to read byte data from the address to be verified (the previously programmed address) in the second bus cycle, the content that has actually been written to the address is read out from the memory. the cpu compares this read data with the data that it previously wrote to the address using the program command. if the compared data do not match, the user need to execute the program and program-verify operations one more time. erase command (20 16 + 20 16 ) the flash memory control circuit executes an erase operation by writing command code 20 16 to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. the erase operation requires approximately 20 ms. wait for 20 ms or more before the user go to the next processing. before this erase command can be performed, all memory locations to be erased must have had data 00 16 written to by using the program and program-verify commands. during erase operation, the watchdog timer remains idle, with the value 7fff 16 set in it. note 1: the erase operation is not completed immediately by writing an erase command once. the user must always execute an erase-verify command after each erase command executed. and if verification fails, the user need to execute the erase command repeatedly until the verification passes. see figure bb-3 for an example of an erase flowchart. erase-verify command (a0 16 ) the erase-verify mode is entered by writing the command code a0 16 to the flash command register in the first bus cycle. when the user execute an instruction to read byte data from the address to be verified (e.g., lde instruction) in the second bus cycle, the content of the address is read out. the cpu must sequentially erase-verify memory contents one address at a time, over the entire area erased. if any address is encountered whose content is not ff 16 (not erased), the cpu must stop erase-verify at that point and execute erase and erase-verify operations one more time. note 1: if any unerased memory location is encountered during erase-verify operation, be sure to execute erase and erase-verify operations one more time. in this case, however, the user does not need to write data 00 16 to memory before erasing.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer cpu rewrite mode preliminary 132 start address = first location loop counter : x=0 write program command write : 40 16 duration = 20 s duration = 6 s x=25 ? verify ok ? pass fail fail pass yes pass no no fail write program data/ address loop counter : x=x+1 write program verify command last address ? next address ? write read command write read command verify ok ? write : program data write : c0 16 write : 00 16 write:20 16 duration = 6s x=1000 ? verify ok? pass fail fail pass yes pass no no fail duration = 20ms yes no start all bytes = "00 16 "? program all bytes = "00 16 " address = first address loop counter x=0 write erase command write erase command loop counter x=x+1 write erase verify command/address verify ok? last address? next address write read command write read command write:20 16 write:a0 16 write:00 16 read: expect value=ff 16 figure bb-3. program and erase execution flowchart in the cpu rewrite mode program erase reset command (ff 16 + ff 16 ) the reset command is used to stop the program command or the erase command in the middle of operation. after writing command code 40 16 or 20 16 twice to the flash command register, write command code ff 16 to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. the program command or erase command is disabled, with the flash memory placed in read mode.
appendix parallel i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 133 pin name signal name i/o function v cc ,v ss power supply input apply 5 v 10 % to the vcc pin and 0 v to the vss pin. cnv ss cnv ss apply 12 v 5 % to the cnv ss pin. i reset reset input connect this pin to v ss . i x in clock input connect a ceramic or crystal resonator between the x in and x out pins. when entering an externally derived clock, enter it from x in and leave x out open. i x out clock output o av cc , av ss analog power supply input v ref reference voltage input i connect av ss to vss and avcc to vcc, respectively. connect this pin to v ss . p0 0 to p0 7 data i/o d 0 to d 7 these are data d 0 ? 7 input/output pins. these are address a 4 ? 7 input pins. i p3 0 to p3 3 p3 4 to p3 5 i p4 1 this is a oe input pin. i p5 0 address input a 17 p6 4 to p6 7 i/o address input a 4 to a 7 input port p3 oe input p4 2 , p4 4 , p4 5 input port p4 i enter high signals or low signals to these pins. input port p6 enter high signals or low signals to these pins. i p7 0 to p7 1 input port p7 i ce input this is a ce input pin. i p4 3 enter low signals to these pins. p4 0 we input this is a we input pin. i i this is address a 17 input pin. p5 1 v rfy input i apply v ih (5 v) to this pin when v pp = v pph (12 v), or v il (0 v) when v pp = v ppl (5 v). p5 2 i input port p5 enter low signal to this pin. p5 3 , p5 4 input port p5 i enter high signals or low signals to these pins. these are address a 0 ? 3 input pins. i p6 0 to p6 3 address input a 0 to a 3 enter high signals or low signals to these pins. p1 0 to p1 7 address input a 8 to a 15 these are address a 8 ? 15 input pins. i description of pin function (flash memory parallel i/o mode)
appendix parallel i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 134 m30201(flash memory version) m5m28f101 v cc v ss v cc v ss v cc v ss address input data i/o oe input ce input p6 0 to p6 3 , p3 0 to p3 3 , p1 0 to p1 7 , p5 0 p0 0 to p0 7 p4 1 p4 3 a 0 to a 15 , a 17 d 0 to d 7 oe ce we input v rfy input (note) p4 0 p5 1 we note: the v rfy input only selects read-only or read/write mode, and does not have any pin associated with it on the m5m28f101. parallel i/o mode the parallel i/o mode is entered by making connections shown in figures cc-2 and cc-3 and then turning the v pph power supply on. in this mode, the m30201 (flash memory version) operates in a manner similar to the nor flash memory m5m28f101 from mitsubishi. note, however, that there are some differences with regard to the functions not available with the microcomputer (function of read device identification code) and matters related to memory capacity. table cc-2 shows pin relationship between the m30201 and m5m28f101 in parallel i/o mode. table cc-2. pin relationship in parallel i/o mode sfr ram sfr ram sfr ram 00000 16 00400 16 yyyyy 16 df000 16 dfdff 16 xxxxx 16 fffff 16 m30201f6 xxxxx 16 f4000 16 yyyyy 16 00bff 16 microcomputer mode parallel i/o mode cpu rewrite mode standard serial i/o mode boot rom area (3.5k bytes) boot rom area (3.5k bytes) user rom area user rom area user rom area collective erasable/ programmable area type no. note 1: in cpu rewrite and standard serial i/o modes, the user rom is the only erasable/programmable area. note 2: in parallel i/o mode, the area to be erased/programmed can be selected by the address a17 input. the user rom area is selected when this address input is high and the boot rom area is selected when this address input is low. collective erasable/ programmable area collective erasable/ programmable area figure cc-1. block diagram of flash memory version
appendix parallel i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 135 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 v ref x in x out p5 0 /t x d 0 /an 50 p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 v ss reset v cc cnv ss p5 1 /r x d 0 /an 51 p5 2 /clk 0 /an 52 av ss p4 5 /tx2 inout p7 0 /tb0 in /x cout p7 1 /tb1 in /x cin p5 4 /ck out /an 54 p5 3 /clks/an 53 av cc p0 7 /ki 7 p0 6 /ki 6 p0 5 /ki 5 p0 4 /ki 4 p0 3 /ki 3 p0 2 /ki 2 p0 1 /ki 1 p1 0 (led 0 ) p1 1 (led 1 ) p1 2 (led 2 ) p1 3 (led 3 ) p1 4 (led 4 ) p1 5 (led 5 ) p1 6 (led 6 ) p1 7 (led 7 ) m30201f6sp m30201f6tsp p0 0 /ki 0 p3 0 p3 1 p3 2 p3 3 p3 4 p3 5 p4 0 /ta0 in /t x d 1 p4 1 /ta0 out p4 2 /r x d 1 p4 4 /int 1 /tx1 inout p4 3 /int 0 /tx0 inout ce oe we d0 a1 a3 a2 d1 d2 d3 d4 d5 d6 d7 a8 a9 a10 a11 a13 a14 a15 a4 a5 a12 a6 a0 a17 v ss v cc a7 v pph connect oscillator circuit. v rfy figure cc-2. pin connection diagram in parallel i/o mode (1)
appendix parallel i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 136 figure cc-3. pin connection diagram in parallel i/o mode (2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 27 28 x in x out p5 0 /t x d 0 /an 50 p6 7 /an 7 v ss reset v cc cnv ss p5 1 /r x d 0 /an 51 p5 2 /clk 0 /an 52 p4 5 /tx2 inout p7 1 /tb1 in /x cin p7 0 /tb0 in /x cout p4 1 /ta0 out p4 0 /ta0 in /t x d 1 p4 2 /r x d 1 p5 4 /ck out /an 54 p5 3 /clks/an 53 v ref p6 0 /an 0 p6 1 /an 1 av ss av cc p1 0 (led 0 ) p1 4 (led 4 ) m30201f6fp m30201f6tfp n.c. n.c. n.c. n.c. p0 0 /ki 0 p6 2 /an 2 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 p0 1 /ki 1 p0 2 /ki 2 p0 3 /ki 3 p0 4 /ki 4 p0 5 /ki 5 p0 6 /ki 6 p0 7 /ki 7 p1 1 (led 1 ) p1 2 (led 2 ) p1 3 (led 3 ) p1 5 (led 5 ) p1 6 (led 6 ) p1 7 (led 7 ) p3 0 p3 1 p3 2 p3 3 p3 4 p3 5 p4 4 /int 1 /tx1 inout p4 3 /int 0 /tx0 inout a17 d0 d1 d2 d3 d4 d5 d6 d7 a8 a9 a10 a11 a12 a13 a15 a14 a4 a6 a5 a7 v ss v cc ce oe we v rfy v pph connect oscillator circuit. a0 a1 a2 a3
appendix parallel i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 137 read only read/ write read write output disabled stand by read output disabled stand by data output hi-z data output hi-z data input v il v il v ih v il v il v ih v il v ih v il v ih v ih v ih v il v il v il v ih v ih v ih v ih v ih mode pin name ce oe we v rfy d 0 to d 7 note: x can be v il or v ih . v pph v pp v pph v pph v pph v pph v pph v pph x x x x hi-z hi-z v il v ih v il v ih user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in figure cc-1 can be rewritten. in the boot rom area, an erase block operation is applied to only one 4 k byte block. the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the mitsubishi factory. therefore, using the device in standard serial input/output mode, the user does not need to write to the boot rom area. functional outline (parallel i/o mode) in parallel i/o mode, bus operation modesread, output disable, standby, and writeare selected by _____ _____ _____ the status of the ce, oe, we, v rfy , and cnv ss input pins. the contents of erase, program, and other operations are selected by writing a software command. the data in memory can only be read out by a read after software command input. program and erase operations are controlled using software commands. table cc-3. relationship between control signals and bus operation modes
appendix parallel i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 138 the following explains about bus operation modes, software commands, and status register. bus operation modes read-only mode is entered by applying v pph to the cnv ss pin and a low voltage to the v rfy pin. read-only mode has three states: read, output disable, and standby which are selected by _____ _____ ______ setting the ce, oe, and we pins high or low. read-write mode is entered by applying v pph to the cnv ss pin and a high voltage to the v rfy pin. read-write mode has four states: read, output disable, standby, and write which are selected by _____ _____ ______ setting the ce, oe, and we pins high or low. read ______ _____ _____ the read mode is entered by pulling the we pin high when the ce and oe pins are low. in read mode, the data corresponding to each software command entered is output from the data i/o pins d 0 Cd 7 . output disable _____ _____ _____ the output disable mode is entered by pulling the ce pin low and the we and oe pins high. also, the data i/o pins are placed in the high-impedance state. standby _____ the standby mode is entered by driving the ce pin high. also, the data i/o pins are placed in the high-impedance state. write the write mode is entered by applying v pph to the cnv ss pin and a high voltage to the v rfy pin _____ _____ _____ and then pulling the we pin low when the ce pin is low and oe pin is high. in this mode, the device accepts the software commands or write data entered from the data i/o pins. a program, erase, or some other operation is initiated depending on the content of the software command entered here. _____ the input data such as address is latched at the falling edge of we pin. the input data such as _____ software command is latched at the rising edge of we pin.
appendix parallel i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 139 command program verify read program first bus cycle second bus cycle 00 16 40 16 c0 16 write write write program address write read erase verify a0 16 write verify data read erase 20 16 write 20 16 write reset ff 16 write mode address mode address data (d 0 to d 7 ) data (d 0 to d 7 ) x program data verify data ff 16 write x x x x verify address x x x x software commands table cc-4 lists the software commands available with the m30201 (flash memory version). by entering a software command from the data i/o pins (d 0 Cd 7 ) in write mode, specify the content of the operation, such as erase or program operation, to be performed. the following explains the content of each software command. table cc-4. software command list (parallel i/o mode) read command (00 16 ) the read mode is entered by writing the command code 00 16 in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data i/o pins (d 0 Cd 7 ). the read mode is retained intact until another command is written. after reset and after the reset command is executed, the read mode is set. program command (40 16 ) the program mode is entered by writing the command code 40 16 in the first bus cycle. when an address and data to be program is write in the second bus cycle, the flash memory control circuit executes the program operation. the program operation requires approximately 20 m s. wait for 20 m s or more before the user go to the next processing. note 1: the write operation is not completed immediately by writing a program command once. the user must always execute a program-verify command after each program command executed. and if verification fails, the user need to execute the program command repeatedly until the verification passes. see figure cc-4 for an example of a programming flowchart.
appendix parallel i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 140 program-verify command (c0 16 ) the program-verify mode is entered by writing the command code c0 16 in the first bus cycle and the verify data is output from the data i/o pins (d 0 Cd 7 ) in the second bus cycle. erase command (20 16 + 20 16 ) the flash memory control circuit executes an erase operation by writing command code 20 16 in the first bus cycle and the same command code again in the second bus cycle. the erase operation requires approximately 20 ms. wait for 20 ms or more before the user go to the next processing. before this erase command can be performed, all memory locations to be erased must have had data 00 16 written to by using the program and program-verify commands. note 1: the erase operation is not completed immediately by writing an erase command once. the user must always execute an erase-verify command after each erase command executed. and if verification fails, the user need to execute the erase command repeatedly until the verification passes. see figure cc-4 for an example of an erase flowchart. erase-verify command (a0 16 ) the erase-verify mode is entered by writing the command code a0 16 in the first bus cycle and the verify data is output from the data i/o pins (d 0 Cd 7 ) in the second bus cycle. note 1: if any unerased memory location is encountered during erase-verify operation, be sure to execute erase and erase-verify operations one more time. in this case, however, the user does not need to write data 00 16 to memory before erasing.
appendix parallel i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 141 start address = first location loop counter : x=0 write program command write : 40 16 duration = 20 s duration = 6 s x=25 ? verify ok ? pass fail fail pass yes pass no no fail write program data/ address loop counter : x=x+1 write program verify command last address ? next address ? write read command write read command verify ok ? write : program data write : c0 16 write : 00 16 write:20 16 duration = 6s x=1000 ? verify ok? pass fail fail pass yes pass no no fail duration = 20ms yes no start all bytes = "00 16 "? program all bytes = "00 16 " address = first address loop counter x=0 write erase command write erase command loop counter x=x+1 write erase verify command/address verify ok? last address? next address write read command write read command write:20 16 write:a0 16 write:00 16 read: expect value=ff 16 figure cc-4. program and erase execution flowchart in the cpu rewrite mode program erase reset command (ff 16 + ff 16 ) the reset command is used to stop the program command or the erase command in the middle of operation. after writing command code 40 16 or 20 16 twice, write command code ff 16 in the first bus cycle and the same command code again in the second bus cycle. the program command or erase command is disabled, with the flash memory placed in read mode.
appendix parallel i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 142 figure cc-5. protect control address protect function in parallel i/o mode, the internal flash memory has the protect function available. this function protects the flash memory contents from being read or rewritten easily. depending on the content at the protect control address (fffff 16 ) in parallel i/o mode, this function inhibits the flash memory contents against read or modification. the protect control address (fffff 16 ) is shown in figure cc-5 . (this address exists in the user rom area.) the protect function is enabled by setting one of the two protect set bits to 0, so that the internal flash memory contents are inhibited against read or modification. the protect function is disabled by setting both of the two protect reset bits to 00, so that the internal flash memory contents can be read or modified. once the protect function is set, the user cannot change settings of the protect clear bits while in parallel i/o mode. settings of the protect reset bits can only be changed in cpu rewrite mode. symbol address when shipping romcp fffff 16 ff 16 protect control address bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: protect removed 01: protect set bit effective 10: protect set bit effective 11: protect set bit effective 00: protect enabled 01: protect enabled 10: protect enabled 11: protect disabled protect reset bit protect set bit romcr romcp b5 b4 b7 b6 note 1: when protect is turned on, the flash memory version is protected against readout or modification in parallel i/o mode. note 2: the protect reset bits can be used to turn off protect . however, since these bits cannot be changed in parallel i/o mode, they need to be rewritten in cpu rewrite mode. reserved bit always set to "1". 1 1 1 1
appendix standard serial i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 143 pin description v cc ,v ss apply 5v 10 % to vcc pin and 0 v to vss pin. cnv ss apply 12v 5 % to this pin. reset reset input pin. while reset is "l" level, a 20 cycle or longer clock must be input to xin pin. x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out av cc , av ss v ref connect av ss to vss and avcc to vcc, respectively. enter the reference voltage for ad from this pin. p0 0 to p0 7 input "h" or "l" level signal or open. p1 0 to p1 7 input "h" or "l" level signal or open. p3 0 to p3 5 input "h" or "l" level signal or open. p4 0 to p4 5 input "h" or "l" level signal or open. p5 4 input "h" or "l" level signal or open. p5 0 serial data output pin. p5 1 p5 2 serial clock input pin. p5 3 p6 0 to p6 7 input "h" or "l" level signal or open. p7 0 to p7 1 input "h" or "l" level signal or open. name power input cnv ss reset input clock input clock output analog power supply input reference voltage input input port p0 input port p1 input port p3 input port p4 input port p5 txd output sclk input busy output input port p6 input port p7 i/o i i i o i i i i i i i i i i o rxd input serial data input pin. o busy signal output pin. pin functions (flash memory standard serial i/o mode)
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode preliminary 144 figure dd-1. pin connections for serial i/o mode (1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 v ref x in x out p5 0 /t x d 0 /an 50 p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 v ss reset v cc cnv ss p5 1 /r x d 0 /an 51 p5 2 /clk 0 /an 52 av ss p4 5 /tx2 inout p7 0 /tb0 in /x cout p7 1 /tb1 in /x cin p5 4 /ck out /an 54 p5 3 /clks/an 53 av cc p0 7 /ki 7 p0 6 /ki 6 p0 5 /ki 5 p0 4 /ki 4 p0 3 /ki 3 p0 2 /ki 2 p0 1 /ki 1 p1 0 (led 0 ) p1 1 (led 1 ) p1 2 (led 2 ) p1 3 (led 3 ) p1 4 (led 4 ) p1 5 (led 5 ) p1 6 (led 6 ) p1 7 (led 7 ) m30201f6sp m30201f6tsp p0 0 /ki 0 p3 0 p3 1 p3 2 p3 3 p3 4 p3 5 p4 0 /ta0 in /t x d 1 p4 1 /ta0 out p4 2 /r x d 1 p4 4 /int 1 /tx1 inout p4 3 /int 0 /tx0 inout busy sclk r x d t x d v ss v cc cnv ss v ss v cc reset cnv ss v pp h reset v ss v cc mode setup method signal value connect oscillator circuit.
appendix standard serial i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 145 figure dd-2. pin connections for serial i/o mode (2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 27 28 x in x out p5 0 /t x d 0 /an 50 p6 7 /an 7 v ss reset v cc cnv ss p5 1 /r x d 0 /an 51 p5 2 /clk 0 /an 52 p4 5 /tx2 inout p7 1 /tb1 in /x cin p7 0 /tb0 in /x cout p4 1 /ta0 out p4 0 /ta0 in /t x d 1 p4 2 /r x d 1 p5 4 /ck out /an 54 p5 3 /clks/an 53 v ref p6 0 /an 0 p6 1 /an 1 av ss av cc p1 0 (led 0 ) p1 4 (led 4 ) m30201f6fp m30201f6tfp n.c. n.c. n.c. n.c. p0 0 /ki 0 p6 2 /an 2 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 p0 1 /ki 1 p0 2 /ki 2 p0 3 /ki 3 p0 4 /ki 4 p0 5 /ki 5 p0 6 /ki 6 p0 7 /ki 7 p1 1 (led 1 ) p1 2 (led 2 ) p1 3 (led 3 ) p1 5 (led 5 ) p1 6 (led 6 ) p1 7 (led 7 ) p3 0 p3 1 p3 2 p3 3 p3 4 p3 5 p4 4 /int 1 /tx1 inout p4 3 /int 0 /tx0 inout v ss v cc busy sclk r x d t x d cnv ss reset v ss v cc cnv ss v pp h reset v ss v cc mode setup method signal value connect oscillator circuit.
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode preliminary 146 standard serial i/o mode the standard serial i/o mode serially inputs and outputs the software commands, addresses and data necessary for operating (read, program, erase, etc.) the internal flash memory. it uses a purpose-specific serial programmer. the standard serial i/o mode differs from the parallel i/o mode in that the cpu controls operations like rewriting (uses the cpu rewrite mode) in the flash memory or serial input for rewriting data. the standard serial i/o mode is started by clearing the reset with v pph at the cnvss pin. (for the normal microprocessor mode, set cnvss to l.) this control program is written in the boot rom area when shipped from mitsubishi electric. therefore, if the boot rom area is rewritten in the parallel i/o mode, the standard serial i/o mode cannot be used. figures dd-1 and dd-2 show the pin connections for the standard serial i/o mode. serial data i/o uses three uart0 pins: clk 0 , rxd 0 , and txd 0 and port p5 3 (busy). the clk 0 pin is the transfer clock input pin and it transfers the external transfer clock. the txd 0 pin outputs the cmos signal. the p5 3 (busy) pin outputs an l level when reception setup ends and an h level when the reception operation starts. transmission and reception data is transferred serially in 8-byte blocks. in the standard serial i/o mode, only the user rom area shown in figure cc-1 can be rewritten, the boot rom area cannot. the standard serial i/o mode has a 7-byte id code. when the flash memory is not blank and the id code does not match the content of the flash memory, the command sent from the programmer is not accepted. function overview (standard serial i/o mode) in the standard serial i/o mode, software commands, addresses and data are input and output between the flash memory and an external device (serial programmer, etc.) using a clock synchronized serial i/o (uart0) and p5 3 . in reception, the software commands, addresses and program data are synchronized with the rise of the transfer clock input to the clk 0 pin and input into the flash memory via the rxd 0 pin. in transmission, the read data and status are synchronized with the fall of the transfer clock and output to the outside from the txd 0 pin. the txd 1 pin is cmos output. transmission is in 8-bit blocks and lsb first. when busy, either during transmission or reception, or while executing an erase operation or program, the p5 3 (busy) pin is h level. accordingly, do not start the next transmission until the p5 3 (busy) pin is l level. also, data in memory and the status register can be read after inputting a software command. it is pos- sible to check flash memory operating status or whether a program or erase operation ended success- fully or in error by reading the status register. software commands and the status register are explained here following.
appendix standard serial i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 147 software commands table dd-1 lists software commands. in the standard serial i/o mode, erase operations, programs and reading are controlled by transferring software commands via the rxd pin. software commands are explained here below. table dd-1. software commands (standard serial i/o mode) control command 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 page read 2 page program 3 erase all unlocked blocks 4 read status register 5 clear status register 6 read lockbit status 7 id check function 8 download function 9 version data output function 14 boot area output function note1: shading indicates transfer from flash memory microcomputer to serial programmer. all other data is transferred from the serial programmer to the flash memory microcomputer. note2: srd refers to status register data. srd1 refers to status register 1 data. note3: all commands can be accepted when the flash memory is totally blank. when id is not verificate not acceptable not acceptable not acceptable acceptable not acceptable not acceptable acceptable not acceptable acceptable not acceptable version data output to 9th byte data output to 259th byte data output to 259th byte data input to 259th byte to id7 data output data input id1 to required number of times version data output data output data output data input id size data input version data output data output data output data input lock bit data output address (high) check- sum version data output data output address (high) address (high) srd1 output address (high) address (middle) size (high) version data output address (high) address (middle) address (middle) d0 16 srd output address (middle) address (low) size (low) version data output address (middle) ff 16 41 16 a7 16 70 16 50 16 71 16 f5 16 fa 16 fb 16 fc 16
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode preliminary 148 page read command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) send the ff 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first in sync with the rise of the clock. data0 data255 clk0 rxd0 txd0 p5 3 (busy) a 8 to a 15 a 16 to a 23 ff 16 srd output srd1 output 70 16 clk0 rxd0 txd0 p5 3 (busy) figure dd-3. timing for page read read status register command this command reads status information. when the 70 16 command code is sent in the 1st byte of the transmission, the contents of the status register (srd) specified in the 2nd byte of the transmission and the contents of status register 1 (srd1) specified in the 3rd byte of the transmission are read. figure dd-4. timing for reading the status register
appendix standard serial i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 149 figure dd-5. timing for clearing the status register page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page program command as explained here following. (1) send the 41 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respectively. (3) from the 4th byte onward, as write data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is automatically written. when reception setup for the next 256 bytes ends, the p5 3 (busy) signal changes from the h to the l level. the result of the page program can be known by reading the status register. for more information, see the section on the status register. 50 16 clk0 rxd0 txd0 p5 3 (busy) clear status register command this command clears the bits (sr3Csr4) which are set when the status register operation ends in error. when the 50 16 command code is sent in the 1st byte of the transmission, the aforementioned bits are cleared. when the clear status register operation ends, the p5 3 (busy) signal changes from the h to the l level. a 8 to a 15 a 16 to a 23 41 16 data0 data255 clk0 rxd0 txd0 p5 3 (busy) figure dd-6. timing for the page program
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode preliminary 150 read lock bit status command this command reads the lock bit status of the specified block. execute the read lock bit status com- mand as explained here following. (1) send the 71 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) the lock bit data of the specified block is output in the 4th byte of the transmission. write the highest address of the specified block for addresses a 8 to a 23 . the m30201 (flash memory version) does not have the lock bit, so the read value is always 1 (block unlock). a 8 to a 15 a 16 to a 23 71 16 dq6 clk0 rxd0 txd0 p5 3 (busy) figure dd-8. timing for reading lock bit status erase all unlocked blocks command this command erases the content of all blocks. execute the erase all unlocked blocks command as explained here following. (1) send the a7 16 command code in the 1st byte of the transmission. (2) send the verify command code d0 16 in the 2nd byte of the transmission. with the verify com- mand code, the erase operation will start and continue for all blocks in the flash memory. when block erasing ends, the p5 3 (busy) signal changes from the h to the l level. the result of the erase operation can be known by reading the status register. a7 16 d0 16 clk0 rxd0 txd0 p5 3 (busy) figure dd-7. timing for erasing all unlocked blocks
appendix standard serial i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 151 download command this command downloads a program to the ram for execution. execute the download command as explained here following. (1) send the fa 16 command code in the 1st byte of the transmission. (2) send the program size in the 2nd and 3rd bytes of the transmission. (3) send the check sum in the 4th byte of the transmission. the check sum is added to all data sent in the 5th byte onward. (4) the program to execute is sent in the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. fa 16 program data program data data size (high) data size (low) check sum clk0 rxd0 txd0 p5 3 (busy) figure dd-9. timing for download
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode preliminary 152 version information output command this command outputs the version information of the control program stored in the boot area. execute the version information output command as explained here following. (1) send the fb 16 command code in the 1st byte of the transmission. (2) the version information will be output from the 2nd byte onward. this data is composed of 8 ascii code characters. figure dd-10. timing for version information output boot area output command this command outputs the control program stored in the boot area in one page blocks (256 bytes). execute the boot area output command as explained here following. (1) send the fc 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first, in sync with the rise of the clock. fb 16 'x' 'v' 'e' 'r' clk0 rxd0 txd0 p5 3 (busy) data0 data255 a 8 to a 15 a 16 to a 23 fc 16 clk0 rxd0 txd0 p5 3 (busy) figure dd-11. timing for boot area output
appendix standard serial i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 153 id check this command checks the id code. execute the boot id check command as explained here following. (1) send the f5 16 command code in the 1st byte of the transmission. (2) send addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 of the 1st byte of the id code in the 2nd, 3rd and 4th bytes of the transmission respectively. (3) send the number of data sets of the id code in the 5th byte. (4) the id code is sent in the 6th byte onward, starting with the 1st byte of the code. id size id1 id7 f5 16 df 16 ff 16 0f 16 clk0 rxd0 txd0 p5 3 (busy) figure dd-12. timing for the id check id code when the flash memory is not blank, the id code sent from the serial programmer and the id code written in the flash memory are compared to see if they match. if the codes do not match, the com- mand sent from the serial programmer is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , and 0ffff7 16 . write a program into the flash memory, which already has the id code set for these addresses. reset watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector 0fffff 16 to 0ffffc 16 0ffffb 16 to 0ffff8 16 0ffff7 16 to 0ffff4 16 0ffff3 16 to 0ffff0 16 0fffef 16 to 0fffec 16 0fffeb 16 to 0fffe8 16 0fffe7 16 to 0fffe4 16 0fffe3 16 to 0fffe0 16 0fffdf 16 to 0fffdc 16 4 bytes address figure dd-13. id code storage addresses
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode preliminary 154 status register (srd) the status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. it can be read by writing the read status register command (70 16 ). also, the status register is cleared by writing the clear status register command (50 16 ). table dd-2 gives the definition of each status register bit. after clearing the reset, the status register outputs 80 16 . table dd-2. status register (srd) status bit (sr7) the status bit indicates the operating status of the flash memory. when power is turned on, 1 (ready) is set for it. the bit is set to 0 (busy) during an auto write or auto erase operation, but it is set back to 1 when the operation ends. erase bit (sr5) the erase bit reports the operating status of the auto erase operation. if an erase error occurs, it is set to 1. when the erase status is cleared, it is set to 0. program bit (sr4) the program bit reports the operating status of the auto write operation. if a write error occurs, it is set to 1. when the program status is cleared, it is set to 0. srd0 bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) status name status bit reserved erase bit program bit reserved reserved reserved reserved definition "1" "0" ready - terminated in error terminated in error - - - - busy - terminated normally terminated normally - - - -
appendix standard serial i/o mode preliminary under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 155 status register 1 (srd1) status register 1 indicates the status of serial communications, results from id checks and results from check sum comparisons. it can be read after the srd by writing the read status register command (70 16 ). also, status register 1 is cleared by writing the clear status register command (50 16 ). table dd-3 gives the definition of each status register 1 bit. 00 16 is output when power is turned on and the flag status is maintained even after the reset. table dd-3. status register 1 (srd1) boot update completed bit (sr15) this flag indicates whether the control program was downloaded to the ram or not, using the down- load function. check sum consistency bit (sr12) this flag indicates whether the check sum matches or not when a program, is downloaded for execu- tion using the download function. id check completed bits (sr11 and sr10) these flags indicate the result of id checks. some commands cannot be accepted without an id check. data reception time out (sr9) this flag indicates when a time out error is generated during data reception. if this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. srd1 bits sr15 (bit7) sr14 (bit6) sr13 (bit5) sr12 (bit4) sr11 (bit3) sr10 (bit2) sr9 (bit1) sr8 (bit0) status name boot update completed bit reserved reserved checksum match bit id check completed bits data receive time out reserved definition "1" "0" update completed - - match 00 01 10 11 not update - - mismatch normal operation - not verified verification mismatch reserved verified time out -
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode preliminary 156 example circuit application for the standard serial i/o mode the below figure shows a circuit application for the standard serial i/o mode. control pins will vary ac- cording to programmer, therefore see the programmer manual for more information. p5 3 (busy) clk0 r x d0 t x d0 cnvss clock input p5 3 output data input data output m30201 flash memory version (1) control pins and external circuitry will vary according to programmer. for more information, see the programmer manual. (2) in this example, the microprocessor mode and standard serial i/o mode are switched via a switch. v pp figure dd-14. example circuit application for the standard serial i/o mode
under development mitsubishi microcomputers m30201 group single-chip 16-bit cmos microcomputer 157 sdip52-p-600-1.78 weight(g) jedec code 5.1 eiaj package code lead material alloy 42/cu alloy 52p4b plastic 52pin 600mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 ?.8 0.4 0.5 0.6 0.9 1.0 1.3 0.65 0.75 1.05 0.22 0.27 0.34 45.65 45.85 46.05 12.85 13.0 13.15 1.778 15.24 3.0 0 ?5 5.5 e e 1 52 27 26 1 e c e 1 a 2 a 1 b b 1 b 2 e l a seating plane d qfp56-p-1010-0.65 0.59 weight(g) jedec code eiaj package code lead material alloy 42 56p6s-a plastic 56pin 10 5 10mm body qfp symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.2 0.1 0.35 i 2 1.3 m d 10.6 m e 10.6 10 0 0.1 1.4 0.8 0.6 0.4 13.1 12.8 12.5 13.1 12.8 12.5 0.65 10.2 10.0 9.8 10.2 10.0 9.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 0 3.05 e e e e c h e 1 56 43 28 42 29 15 14 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f
keep safety first in your circuit designs! notes regarding these materials l mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. l these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. l mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. l all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http:// www.mitsubishichips.com). l when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. l mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. l if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. l please contact mitsubishi electric corporation or an authorized mitsubishi semicon ductor product distributor for further details on these materials or the products con tained therein.
mitsubishi semiconductors m30201 group data sheet rev.d april first edition 1998 july second edition 1998 february third edition 1999 may fourth edition 1999 editioned by committee of editing of mitsubishi semiconductor data sheet published by mitsubishi electric corp., kitaitami works this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1999 mitsubishi electric corporation

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